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本科毕业设计外文文献翻译
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题 目:Packet Handling Hardware Support 学生姓名: 学 院: 系 别: 专 业: 班 级: 指导教师:
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内蒙古工业大学本科毕业设计外文文献翻译
Packet Handling Hardware Support
参考文献:Texas Instruments.CC1101 Low-Power Sub-1 GHz RF Transceiver.www. ti.com. 2013
The CC1101 has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO:
A programmable number of preamble bytes
A two byte synchronization (sync) word. Can be duplicated to give a 4-byte
sync word (recommended). It is not possible to only insert preamble or only insert a sync word
A CRC checksum computed over the data field.
The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate where the recommended preamble length is 8 bytes. In addition, the following can be implemented on the data field and the optional 2-byte CRC checksum:
Whitening of the data with a PN9 sequence
Forward Error Correction (FEC) by the use of interleaving and coding of the
data (convolutional coding)
In receive mode, the packet handling support will de-construct the data packet by implementing the following (if enabled):
Preamble detection Sync word detection
CRC computation and CRC check One byte address check
Packet length check (length byte checked against a programmable maximum
length) De-whitening
De-interleaving and decoding
Optionally, two status bytes (see Table 27 and Table 28) with RSSI value, Link Quality Indication, and CRC status can be appended in the RX FIFO.
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内蒙古工业大学本科毕业设计外文文献翻译
Table 27: Received Packet Status Byte 1(first byte appended after the data) Bit Field Name Description 7:0 RSSI RSSI value Table 28: Received Packet Status Byte 2(second byte appended after the data) Bit Field Name Description 7 CRC_OK 1:CRC for received data OK (or CRC disabled) 0:CRC error in received data 6:0 Indicating the link quality Note: Register fields that control the packet handling features should only be altered when CC1101 is in the IDLE state. LQI 1. Data whitening
From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (on data dependencies).
Real data often contain long sequences of zeros and ones. In these cases, performance can be improved by whitening the data before transmitting, and de-whitening the data in the receiver.
With CC1101, this can be done automatically. By setting PKTCTRLO. WHITE_DATA=1, all data, except the preamble and the sync word will be XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted. This is shown in Figure 16. At the receiver end, the data are XOR-ed with the same pseudorandom sequence. In this way, the whitening is reversed, and the original data appear in the receiver. The PN9sequence is initialized to all 1’s.
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内蒙古工业大学本科毕业设计外文文献翻译
2. Packet Format
The format of the data packet can be configured and consists of the following items (see Figure 17):
Preamble
Synchronization word Optional length byte Optional address byte Payload
Optional 2 byte CRC
The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable through the value of MDMCFG1.NUM_PREAMBLE. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been
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内蒙古工业大学本科毕业设计外文文献翻译
transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue ro send preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word and then the data bytes.
The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the AYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by setting MDMCFG2.SYNC_MODE to 3 or 7. The sync word will then be repeated twice. CC1101 supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.
Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG =0. The desired packet length is set by the PKTLEN register. This value must be different from 0.
In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and optional CRC. The PKTLEN register is used to set the maximum packet length allowed in RX. Any packet received with a length byte with a value greater than PKTLEN will be discarded. The PKTLEN value must be different from 0. The byte written to the TXFIFO must be different from 0.
With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception will continue until turned off manually. As described in the next section, this can be used to support packet formats with different length configuration than natively supported by CC1101. one should make sure that TX is not turn off during the transmission of the first half of any byte. Refer to the CC1101 Errata Notes [4] for more details. Note: The minimum packet length supported (excluding the optional length byte and CRC) is one byte of payload data. 4
内蒙古工业大学本科毕业设计外文文献翻译
2.1 Arbitrary Length Field Configuration
The packet length register, PKTLEN, can be reprogrammed during receive and transmit. In combination with fixed packet length mode (PKTCTRL0. LENGTH_CONFIG=0), this opens the possibility to have a different length field configuration can supported for variable length packets (in variable packet length mode the length byte is the first byte after the sync word). At the start of reception, the packet length is set a large value. The MCU reads out enough bytes to interpret the length field in the packet. Then the PKTLEN value is set according to this value. The end of packet will occur when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the MCU must be able to program the correct length, before the internal counter reaches the packet length. 2.2 Packet Length >255
The packet automation control register, PKTCTRL0, can be reprogrammed during TX and RX. This opens the possibility to transmit and receive packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0. LENGTH_CONFIG=2) must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode. When the internal byte counter reaches the PKTLEN value, the transmission or reception ends(the radio enters the state determined
by
TXOFF_MODE
or
RXOFF_MODE).
Automatic
CRC
appending/checking can also be used(by setting PKTCTRL0.CRC_EN=1).
When for example a 600-byte packet is to be transmitted, the MCU should do the following(see also Figure 18)
Set PKTCTRL0.LENGTH_CONFIG=2.
Pre-program the PKTLEN register to mod(600,256)=88.
Transmit at least 345 bytes(600-255), for example by filling the -byte TX FIFO
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内蒙古工业大学本科毕业设计外文文献翻译
six times(384 bytes transmitted). Set PKTCTRL0.LENGTH_CONFIG=0.
The transmission ends when the packet counter reaches 88. a total of 600 bytes
are transmitted.
3 Packet filtering in Receive Mode
CC1101 supports three different types of packet-filtering; address filtering, maximum length filtering, and CRC filtering. 3.1 Addressing Filtering
Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0*00 broadcast address when PKTCTRL1.ADR_CHK=10 or both the 0*00 and 0*FF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is received and written into the RX FIFO. If the address match fails, the packet is discarded and receive mode restarted(regardless of the MCSM1.RXOFF_MODE setting).
If the received address matches a valid address when using infinite packet length mode and address filtering is enabled, 0*FF will be written into the RX FIFO followed by the address byte and then the payload data.
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内蒙古工业大学本科毕业设计外文文献翻译
3.2Maximum Length Filtering
In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted(regardless of the MCSM1.RXOFF_MODE setting).
3.3 CRC Filtering
The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1.CRC_AUTOFLUSH=1. The CRC auto flush function will flush the entire RX FIFO if the CRC check fails. After auto flushing the RX FIFO, the next state depends on the MCSM1.RXOFF_MODE setting.
When using the auto flush function, the maximum packet length is 63 bytes in variable packet length mode. Note that when PKTCTRL1APPEND_STATUS is enabled, the maximum allowed packet length is reduced by two bytes in order to make room in the RX FIFO for the two status bytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet. The MCU must not read from the current packet until the CRC has been checked as OK. 4 Packet Handling in Transmit Mode
The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet(including the optional address byte). If address recognition is enabled on the receiver, the second byte written to the TX FIFO must be the address byte.
If fixed packet length is enabled, the first byte written to the TX FIFO should be the address(assuming the receiver uses address recognition).
The modulator will first send the programmed number of preamble bytes. If data is avaible in the TX FIFO, the modulator will send the two-bytes(optionally 4-byte)
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内蒙古工业大学本科毕业设计外文文献翻译
sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has been underflowed will not restart TX mode.
If whitening is enabled, everything following the sync words will be whitened. This is done before the optional FEC/interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1.
If FEC/interleaving is enabled, everything following the sync words will be scrambled by the interleaver and FEC encoded before being modulated. FEC is enabled by setting MDMCFG1.FEC_EN=1. 5 Packet Handling in Receive Mode
In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the synchronism and will receive the first payload byte.
If FEC/interleaving is enabled, the FEC decoder will start to decode the first payload byte. The intrerleaver will de-scramble the bits before any other processing is done to the data.
If whitening is enabled, the data will be de-whitened at this stage.
When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed number of bytes.
Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appended CRC checksum.
At the end of the payload, the packet handler will optionally white two extra packet status bytes(see Table27 and Table28) that contain CRC status, link quality indication, and RSSI value.
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6 Packet Handling in Firmware
When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer than bytes, the RX FIFO needs to be refilled white in TX. This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively. There are two possible solutions to get the necessary status information:
a) Interrupt Driven Solution
The GDO pins can be used in both RX and TX to give an interrupt when a sync word has been received/transmitted or when a complete packet has been received/transmitted by setting IOFGX.GDOx_CFG=0*06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the RX FIFO and TX FIFO respectively. The IOCFGx.GDOx_CFG=0*02 and IOCFGx.GDOx_CFG=0*03 configurations are associated with the TX FIFO. See Table 41 for more information. b) SPI Polling
The PKTSTSTUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES and TXBYTES registers can be polled at a given rate to get information about the number of bytes in the RX FIFO and TX FIFO respectively. Alternatively, the number of bytes in the RX FIFO and the TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus. It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 10.3 and the CC1101 Errata Notes[4], when using SPI polling, there is a small, but finite, probability that a single read from registers PKSTATUS, RXBYTES and TXBYTES is being corrupt. The same is the case when reading the chip status byte. Refer to the TI website for SW examples ([9] and [10]).
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数据包处理的硬件支持
CC1101 提供了对数据包导向无线协议的内置硬件支持。
在发送模式下,可对数据包处理器进行配置,以添加如下要素到存储于 TX FIFO内的数据包中:
一个可编程前导字节数
一个二字节(同步)字。可将其复制以生成一个 4 字节同步字(推荐)。
不可能只插入前导或者只插入一个同步字。 通过数据字段计算的 CRC 校验和。
建议设置为 4 字节前导和 4 字节同步字,建议前导长度为 8 字节的 500kBaud 数据速率除外。另外,数据字段和可选 2 字节 CRC 校验和可执行下列操作:
利用 PN9 序列进行数据白化
通过使用数据交错和编码(卷积码)实现前向纠错 (FEC)
接收模式下,数据包处理支持功能将通过执行如下操作(如果已开启)解析数据包:
前导检测 同步字检测
CRC 计算与 CRC 校验 一字节地址检查
数据包长度检查(对可编程最大长度进行长度字节检查) 去白
去交错与解码
可以选择将两个带有 RSSI 值、链路质量指示以及 CRC 状态的状态字节(请参见表 27 和表 28)都加入 RX FIFO 中。
表 27 接收数据包状态字节 1(数据后添加的第一个字节)
位 7:0 字段名称 RSSI 描述 RSSI 值 10
内蒙古工业大学本科毕业设计外文文献翻译
表 28 接收数据包状态字节2(数据后添加的第二个字节)
位 7 字段名称 CRC_OK 描述 1: 接收数据OK(或 CRC 关闭)的 CRC 0: 接收数据中的 CRC 错误 表示链路质量
6:0 LQI 请注意:控制数据包处理特性的寄存器域只有在 CC1101 处于 IDLE 状态下时才可更改。 1 数据白化
从无线通信角度来看,无线数据传输的理想情况是随机和 DC 自由。这就带来了在占用带宽上最为均匀的功率分配的问题,同时也带来了接收机统一工作条件下(无数据相关性)的调节环路。
实际数据通常会包含许多 0 和 1 的长序列。在这种情况下,通过在发送以前白化数据,以及在接收机中去白数据,便可提高性能。
有了
CC1101,这项工作可自动地完成。通过设置
PKTCTRL0.WHITE_DATA=1,除前导和同步字以外的所有数据在发送前将通过一个 9 位伪随机 (PN9) 序列进行异或运算,如图 16 所示。在接收机端,数据由相同的伪随机序列进行异或运算。同样,将白化数据反过来运算,便可在接收机中得到原始数据。PN9 序列被全部初始化为 1。
图 16 TX 模式下的数据白化
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2 数据包格式
可以对数据包格式进行配置,其由如下各项组成(请参见图 17): 前导 同步字 可选长度字节 可选地址字节 有效负载 可选 2 字节 CRC
图 17 数据包格式
前导的形式是一个交互的 0、1 序列(01010101……)。前导的最小长度是可以通过 MDMCFG1.NUM_PREAMBLE 的值进行编程的。当开启 TX 模式时,调制器将开始发送前导。当编程的前导字节数被发送完毕时,调制器就开始发送同步字,然后发送来自 TX FIFO 的数据(如果是有效数据的话)。若 TX FIFO 为空,调制器将继续发送前导字节,直到第一个字节被写入 TX FIFO 为止。调制器随后将发送同步字,然后发送数据字节。
同步字是设置于 SYNC1 和 SYNC0 两个寄存器中的 2 字节值。同步字提供了输入数据包的字节同步。一个一字节同步字可通过设置前导形式的 SYNC1值来仿真。通过设置 MDMCFG2.SYNC_MODE=3 或 7 亦可能仿真一个 32位同步字。该同步字随后将被重复 2 次。
CC11001 可支持固定数据包长度协议和可变数据包长度协议。可变或固定数据包长度模式可用于长达 255 字节的数据包。对更长的数据包而言,必须使用无长度的数据包模式。
通过设置 PKTCTRL0.LENGTH_CONFIG=0,可选择固定数据包长度模式。理想的数据包长度由 PKTLEN 寄存器来设置。这个值必须不同于0。
在可变数据包长度模式下,即 PKTCTRL0.LENGTH_CONFIG=1,通过同步字后面的第一个字节来配置数据包长度。数据包长度被定义为有效负载数据,但
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不包括长度字节和可选 CRC。PKTLEN 寄存器用于设置RX 模式中允许的最大数据包长度。任何长度字节值大于 PKTLEN 的接收数据包将被丢弃。
PKTCTRL0.LENGTH_CONFIG=2 时,数据包长度设置为无限,发送和接收工作将继续进行,直到手动关闭为止。如下节所述,其可用于支持那些 CC1100E本不支持的不同长度配置的数据包格式。您应该确定,TX 模式在任何字节前半部分发送过程中都没有关闭。详情请参见 CC1101 勘误表说明[4]。
请注意:支持的最小数据包长度(不包括可选长度字节和 CRC)为有效负载数 据的一个字节。 2.1 任意长度域配置
可在接收和发送期间对数据包长度寄存器 PKTLEN 重新编程。结合固定数据包长度模式 (PKTCTRL0.LENGTH_CONFIG=0),此举实现了支持可变长度数据包以外不同长度域配置的可能性(在可变包长度模式下,长度字节就是同步字之后的第一个字节)。在接收之初,数据包长度设置为一个较大的值。MCU 读出足够的字节以解释数据包中的长度域。然后,根据这个值来设定 PKTLEN 值。当数据包处理器中的字节计数器相当于 PKTLEN 寄存器时,便到达了数据包的末端。因此,在内部计数器到达数据包长度值之前,MCU 必须要能够编程正确的长度值。
2.2 数据包长度>255
数据包自动控制寄存器 PKTCTRL0 可以在 TX 和 RX 模式下完成重新编程,这样一来就使得发送和接收长于 256 字节的数据包成为可能,并且还可以利用数据包处理硬件支持。在数据包一开始,必须激活无限数据包长度模式(PKTCTRL0.LENGTH_CONFIG=2)。在 TX 端,将 PKTLEN 寄存器设置为mod (length,256)。在 RX 端,MCU 读取足够的字节以解释数据包中的长度域,并将 PKTLEN 寄存器设置为 mod (length,256)。当数据包剩余字节少于256 字节时,MCU 关闭无限数据包长度模式,并开启固定数据包长度模式。当内部字节计数器达到 PKTLEN 值时,则发送或接收终止(无线电设备进入由TXOFF_MODE 或 RXOFF_MODE 决定的状态)。另外,还可使用自动 CRC添
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内蒙古工业大学本科毕业设计外文文献翻译
加/校验(通过设置 PKTCTRL0.CRC_EN=1)。
例如,当发送一个 600 字节的数据包时,MCU 应完成如下步骤: 设置 PKTCTRL0.LENGTH_CONFIG=2
预编程 PKTLEN 寄存器为 mod (600,256) = 88
发送至少 345 字节(600 – 255),例如填充 字节 TX FIFO 六次(发 送了 384 字节)。
设置 PKTCTRL0.LENGTH_CONFIG=0
数据包计数器达到 88 时结束发送。总计发送了 600 字节。
数据包处理器的内部字节计数器从 0 计数到 255,然后再从 0 开始计数。
图 18 数据包长度>255
3 接收模式下的数据包滤波
CC1100E 支持三种不同类型的数据包滤波:地址滤波,最大长度滤波,CRC 滤波。
3.1 地址滤波
设置 PKTCTRL1.ADR_CHK 为 0 以外的任何值便可开启数据包地址滤波器。该包处理器引擎会将数据包中的目标地址字节与 ADDR 寄存器中的编程节点地址,以及 PKTCTRL1.ADR_CHK=10 时的 0x00 广播地址或者PKTCTRL1.ADR_CHK=11 时的 0x00 和 0Xff 广播地址进行比较。如果接收到的地址匹配一个有效地址,则接收该数据包,并将其写入 RX FIFO。如果地址匹配失败, 则丢弃该数据包, 并重新启动接收模式( 与MCSM1.RXOFF_MODE 设置无关)。
使用无限数据包长度模式并且地址滤波开启时,如果接收到的地址匹配一个有效地址,那么 0xFF 便会被写入 RX FIFO,之后是地址字节,最后是有效负
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内蒙古工业大学本科毕业设计外文文献翻译
载数据。
3.2 最大长度滤波
在 可 变 数 据 包 长 度 模 式 下 , 即 PKTCTRL0.LENGTH_CONFIG = 1 ,PKTLEN.PACKET_LENGTH 寄存器值用于设置最大允许的数据包长度。如果接收到的长度字节具有一个比该允许的长度更大值,则丢弃该数据包,并且重新启动接收模式(与 MCSM1.RXOFF_MODE 设置无关)。
3.3 CRC 滤波
如果 CRC 校验失败,则设置 PKTCTRL1.CRC_AUTOFLUSH=1 来开启数据包滤波。如果 CRC 校验失败,CRC 自动刷新功能将会刷新整个 RX FIFO。自动刷新 RX FIFO 以后,后面的状态则取决于 MCSM1.RXOFF_MODE 的设置。
当使用自动刷新功能时,可变数据包长度模式下的最大数据包长度为 63 字节,而固定数据包长度模式下则为 字节。请注意, 开启PKTCTRL1.APPEND_STATUS 之后,最大允许的数据包长度减小 2 字节,目的是在 RX FIFO 中为数据包末尾添加的 2 个状态字节留出空间。由于 CRC校验失败时整个 RX FIFO 被刷新,之前接收到的数据包必须在接收当前数据包以前从 FIFO 读取出来。在 CRC 校验为 OK 以前,MCU 不能读取当前数据包。
4 发送模式下的数据包处理
必须要将即将要被发送的有效负载写入 TX FIFO 中。开启可变数据包长度以后,长度字节必须最先被写入。长度字节具有一个与数据包有效负载相当的值(包括可选地址字节)。如果接收机端开启了地址识别,则写入 TX FIFO 的第二个字节必须为地址字节。如果开启了固定数据包长度,则写入 TX FIFO 的第一个字节应为地址字节(假设接收机使用了地址识别)。
调制器会首先发送编程的前导字节数。如果 TX FIFO 中的数据可用,则调制器会发送 2 字节(可选 4 字节)同步字,之后是 TX FIFO 中的有效负载。如果开启了 CRC,则在所有取自 TX FIFO 的数据上计算校验和,并在有效负载之后以 2 个额外字节发送该结果。如果 TX FIFO 在发送完全部数据包以前变为空,那么该无线电设备将进入 TXFIFO_UNDERFLOW 状态。退出该状态
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内蒙古工业大学本科毕业设计外文文献翻译
的唯一方法是发出一个 SFTX 选通脉冲。
在出现下溢以后对 TX FIFO 进行写操作并不会重启 TX 模式。
如果开启了数据白化功能,则同步字之后的所有数据将被白化。这一工作在可选FEC/交错以前便完成。可将 PKTCTRL0.WHITE_DATA 设置为 1 来开启数据白化功能。
如果开启了 FEC/交错,同步字之后的所有数据将被调制以前编码的交错和 FEC 加密编码。将 MDMCFG1.FEC_EN 设置为 1 便可开启 FEC。
5 接收模式下的数据包处理
在接收模式下,解调器和数据包处理器将会搜索一个有效的前导和同步字。如果找到,解调器就获得了位和字节同步机制,并将接收第一个有效负载字节。若 FEC/交错开启,则 FEC 解码器将开始对第一个有效负载字节进行解码。交错器将在任何其他数据处理过程之前对这些位进行解密。
如果白化功能开启了,则在这个阶段数据将被去白。
当可变数据包长度模式开启时,则第一个字节为长度字节。数据包处理器把这个值作为数据包长度存储,并接收该长度字节显示数目的字节。如果使用了固定数据包长度模式,则数据包处理器将会接受编程数目的字节。
接下来,数据包处理器随意地校验地址,并在地址匹配时才继续进行接收。若自动 CRC 校验开启,则数据包处理器会计算 CRC,并将其与附加 CRC 校验和相匹配。
在有效负载末端,数据包处理器将随意写入 2 个包含 CRC 状态、链路质量指示和 RSSI 值的额外数据包状态字节(请参见表 25 和表 26)。
6 固件中的数据包处理
在固件中执行数据包导向无线协议时,MCU 需要知道一个数据包何时被接收到/发送出去。另外,数据包长度大于 字节时,需要在 RX 模式下读取 RXFIFO,需要在 TX 模式下重填 TX FIFO。这就是说,MCU 需要知道能够写入RX FIFO 和 TX FIFO 或从 RX FIFO 和 TX FIFO 读取的字节。获得该必要状态信息的解决方案有如下两种:
a) 中断驱动法
当通过设置 IOCFGx.GDOx_CFG=0x06 接收到/发送出一个同步字或接收到
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内蒙古工业大学本科毕业设计外文文献翻译
/发送出一个完整数据包时,在 RX 和 TX 模式下均可使用 GDO 引脚来实现中断。另外,IOCFGx.GDOx_CFG 寄存器具有两种配置,可用作中断源,从而提供 RX FIFO 和 TX FIFO 中分别有多少个字节的相关信息。
IOCFGx.GDOx_CFG=0x00 和 IOCFGx.GDOx_CFG=0x01 两种配置与 RXFIFO 相关,而 IOCFGx.GDOx_CFG=0x02 和 IOCFGx.GDOx_CFG=0x03 则与 TX FIFO 相关。
b) SPI 轮询
可以某个给定速率对 PKTSTATUS 寄存器轮询,以获取 GDO2 和 GDO0 当前值的相关信息。可以某个给定速率对 RXBYTES 和 TXBYTES 寄存器轮询,以获取 RX FIFO 和 TX FIFO 中所含字节数的相关信息。另外,在 SPI 总线上每发送一个报头字节、数据字节或指令选通脉冲时,可从 MISO 线路上返回的芯片状态字节读取到 RX FIFO 和 TX FIFO 中所含的字节数。
推荐使用中断驱动方法,因为高速 SPI 轮询可降低 RX 灵敏度。而且,如章节10.3 及《CC1100E 勘误表说明》[5] 所述,当使用 SPI 轮询时,存在一定的概率(虽然这种概率较低):单字节读取寄存器 PKTSTATUS、RXBYTES 和TXBYTES 将会失败。读取芯片状态字节时情况相同。请参考 TI 网站上的软件示例([9] 和 [10])。
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