Receiver capable of reducing power consumption in

专利名称：Receiver capable of reducing power

consumption in a PLL circuit

发明人：Yoichiro Minami申请号：US08/136883申请日：19931018公开号：US05396521A公开日：19950307

摘要：In a receiver for use in demodulating a modulated wave modulated by a digitaldata signal arranged within a preselected channel to produce a reproduced data signalby the use of a local frequency signal of a local frequency, a VCO and a PLL circuit areintermittently put into active states with reference to an offset frequency between achannel frequency and the local frequency. The PLL circuit is put into the active state fora time interval determined by the offset frequency before reception of the preselectedchannel while the VCO is put into the active state during the active state of the PLL circuitand during reception of the preselected channel. A duration of the active state in the PLLcircuit becomes long when the offset frequency does not fall within a predeterminedrange determined by predetermined offset frequencies and, otherwise, the duration ofthe active state in the PLL circuit becomes short. The offset frequency is detected by afrequency detector which produces a control signal appearing only when the offsetfrequency is present outside of the predetermined range. The control signal is sent to acontrol circuit for controlling battery saving operations of the VCO and the PLL circuit.

申请人：NEC CORPORATION

代理机构：Sughrue, Mion, Zinn Macpeak & Seas

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