ADS8329IBRSAT资料

BurrĆBrown Productsfrom Texas Instruments

ADS8329ADS8330

SLAS516–DECEMBER2006

LOWPOWER,16-BIT,1-MHz,SINGLE/DUALUNIPOLARINPUT,ANALOG-TO-DIGITAL

CONVERTERSWITHSERIALINTERFACE

FEATURES

•••

2.7-Vto5.5-VAnalogSupply,LowPower:–15.5mW(1MHz,+VA=3V,+VBD=1.8V)1-MHzSamplingRate3V≤+VA≤5.5V,900-kHzSamplingRate2.7V≤+VA≤3VExcellentDCPerformance

–±1.0LSBTyp,±1.75LSBMaxINL–±0.5LSBTyp,±1LSBMaxDNL–16-BitNMCOverTemperature–±0.5mVMaxOffsetErrorat3V–±1mVMaxOffsetErrorat5V

ExcellentACPerformanceatfi=100kHzwith92dBSNR,102dBSFDR,–102dBTHDBuilt-InConversionClock(CCLK)1.65Vto5.5VI/OSupply

–SPI/DSPCompatibleSerial–SCLKupto50MHz

ComprehensivePower-DownModes:–DeepPowerdown–NapPowerdown

–AutoNapPowerdown

UnipolarInputRange:0VtoVrefSoftwareReset

GlobalCONVST(IndependentofCS)ProgrammableStatus/PolarityEOC/INT16-Pin4x4QFNPackageMulti-ChipDaisyChainModeProgrammableTAGBitOutput

Auto/ManualChannelSelectMode(ADS8330)

APPLICATIONS

•••••••

CommunicationsTransducerInterfaceMedicalInstrumentsMagnetometers

IndustrialProcessControlDataAcquisitionSystemsAutomaticTestEquipment

DESCRIPTION

TheADS8329isalowpower,16-bit,1-MSPSanalog-to-digitalconverterwithaunipolarinput.Thedeviceincludesa16-bitcapacitor-basedSARA/Dconverterwithinherentsampleandhold.

TheADS8330isbasedonthesamecoreandincludesa2-to-1inputMUXwithprogrammableoptionofTAGbitoutput.BoththeADS8329andADS8330offerahigh-speed,widevoltageserialinterfaceandarecapableofchainmodeoperationwhenmultipleconvertersareused.

Theseconvertersareavailableina4x4QFNpackageandarefullyspecifiedforoperationovertheindustrial–40°Cto+85°Ctemperaturerange.LowPower,High-SpeedSARConverterFamily

Type/Speed

16BitPseudo-Diff

SingleDual

500kHzADS8327ADS8328

1MHzADS8329ADS8330

•••

•

••••••••

ADS8330+IN1+IN0COMADS8329NC+IN−INREF+REF−+_SAROUTPUTLATCHand3−STATEDRIVERCONVERSIONandCONTROLLOGICSDOCDACCOMPARATOROSCFS/CSSCLKSDICONVSTEOC/INT/CDIPleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

Copyright©2006,TexasInstrumentsIncorporated

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Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

ORDERINGINFORMATION(1)

MODEL

MAXIMUMINTEGRALLINEARITY(LSB)

MAXIMUMDIFFERENTIALLINEARITY(LSB)

MAXIMUMOFFSETERROR(mV)

PACKAGETYPE

PACKAGEDESIGNATOR

TEMPERATURE

RANGE

ORDERINGINFORMATION

TRANSPORTMEDIAQUANTITYSmalltapeand

reel250Tapeandreel

3000Smalltapeand

reel250Tapeandreel

3000Smalltapeand

reel250Tapeandreel

3000Smalltapeand

reel250Tapeandreel

3000

ADS8329IRSAT

ADS8329I

±2.5

–1/+2

±0.8

4X4QFN-16

RSA

–40°Cto85°C

ADS8329IRSARADS8329IBRSAT

ADS8329IB

±1.75

±1

±0.5

4X4QFN-16

RSA

–40°Cto85°C

ADS8329IBRSARADS8330IRSAT

ADS8330I

±2.5

–1/+2

±0.8

4X4QFN-16

RSA

–40°Cto85°C

ADS8330IRSARADS8330IBRSAT

ADS8330IB

±1.75

±1

±0.5

4X4QFN-16

RSA

–40°Cto85°C

ADS8330IBRSAR

(1)

Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIwebsiteatwww.ti.com.

ABSOLUTEMAXIMUMRATINGS

overoperatingfree-airtemperaturerangeunlessotherwisenoted(1)

UNIT

Voltage

+INtoAGND–INtoAGND+VAtoAGND

Voltage

+VBDtoBDGNDAGNDtoBDGND

DigitalinputvoltagetoBDGNDDigitaloutputvoltagetoBDGND

TATstg

Operatingfree-airtemperaturerangeStoragetemperaturerangeJunctiontemperature(TJmax)

Leadtemperature,soldering

4x4QFN-16Package

PowerdissipationθJAthermalimpedance

(1)

Vaporphase(60sec)Infrared(15sec)

–0.3Vto+VA+0.3V–0.3Vto+VA+0.3V

–0.3Vto7V–0.3Vto7V–0.3Vto0.3V–0.3Vto+VBD+0.3V–0.3Vto+VBD+0.3V

–40°Cto85°C–65°Cto150°C

150°C215°C220°C(TJMax-TA)/θJA

47°C/W

Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.

2

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SPECIFICATIONS

TA=–40°Cto85°C,+VA=5V,+VBD=+5.5Vto+1.65V,Vref=5V,fSAMPLE=1MHz(unlessotherwisenoted)

PARAMETER

ANALOGINPUT

Full-scaleinputvoltageAbsoluteinputvoltageInputcapacitanceInputleakagecurrent

Inputchannelisolation,ADS8330only

SYSTEMPERFORMANCE

ResolutionNomissingcodes

INLDNLEO

IntegrallinearityDifferentiallinearityOffseterror(3)Offseterrordrift

EG

GainerrorGainerrordrift

CMRR

CommonmoderejectionratioNoise

PSRRtCONVtSAMPLE1tSAMPLE2

PowersupplyrejectionratioConversiontimeAcquisitiontimeThroughputrateAperturedelayAperturejitterStepresponseOvervoltagerecovery

510100100

ManualtriggerAutotrigger

3

3

1

AtFFFFhoutput

code(3)

SAMPLINGDYNAMICS

18

CCLKCCLKMHznspsnsns

Atdc

VI=0.4Vppat1MHz

ADS8329IB,ADS8330IBADS8329I,ADS8330IADS8329IB,ADS8330IBADS8329I,ADS8330IADS8329IB,ADS8330IBADS8329I,ADS8330I

FSR=5V

–0.25

16–1.75-2.5–1–1–1–1.25

±1.2±1.5±0.4±0.5±0.27±0.80.4–0.040.7570503378

0.251.752.51211.25

16

BitsBitsLSB(2)LSB(2)mVPPM/°C%FSRPPM/°CdBµVRMSdB

Noongoingconversion,DCInputAtdc

VI=±1.25Vppat50kHz

-1

109101

(1)

TESTCONDITIONS

+IN–(–IN)or(+INx–COM)+IN,+IN0,+IN1–INorCOM

MIN0

AGND–0.2AGND–0.2

TYPMAX+Vref

+VA+0.2AGND+0.2

UNITVVpFnAdB

40451

(1)(2)(3)Idealinputspan,doesnotincludegainoroffseterror.LSBmeansleastsignificantbit

Measuredrelativetoanidealfull-scaleinput[+IN–(–IN)]of4.096Vwhen+VA=5V.

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SPECIFICATIONS(continued)

TA=–40°Cto85°C,+VA=5V,+VBD=+5.5Vto+1.65V,Vref=5V,fSAMPLE=1MHz(unlessotherwisenoted)

PARAMETER

DYNAMICCHARACTERISTICSTHD

Totalharmonicdistortion

(4)

TESTCONDITIONS

VIN=5Vppat10kHzVIN=5Vppat100kHzVIN=5Vppat10kHz

ADS8329/30IBADS8329/30I

MINTYP–102–9593

MAXUNIT

dB

SNRSignal-to-noiseratio

VIN=5Vppat100kHzVIN=5Vppat10kHzVIN=5Vppat100kHzVIN=5Vppat10kHzVIN=5Vppat100kHz

90929092901059730

dB

SINADSFDR

Signal-to-noise+distortionSpuriousfreedynamicrange-3dBSmallsignalbandwidth

dBdBMHz

24.55042

MHzMHz

CLOCK

InternalconversionclockfrequencySCLKExternalserialclock

EXTERNALVOLTAGEREFERENCEINPUTVref

InputreferencerangeResistance

(5)

21

UsedasI/Oclockonly

AsI/Oclockandconversionclock5.5V≥+VA≥4.5V

10.3–0.1

Referenceinput

22.9

Vref[REF+–(REF–)](REF–)–AGND

550.1

VkΩ

40

DIGITALINPUT/OUTPUT

Logicfamily—CMOS

VIHVILIICiVOHVOLCOCL

High-levelinputvoltageLow-levelinputvoltageInputcurrentInputcapacitanceHigh-leveloutputvoltageLow-leveloutputvoltageOutputcapacitanceLoadcapacitance

Dataformat—straightbinary

POWERSUPPLYREQUIREMENTS

Powersupplyvoltage

+VBD+VA

1-MHzSamplerate

Supplycurrent

BufferI/OsupplycurrentPowerdissipation

TEMPERATURERANGETA

Operatingfree-airtemperature

–40

85

°C

NapmodePDMode1MSPS

+VA=5V,+VBD=5V+VA=5V,+VBD=1.8V

1.6.5

3.357.00.341.74435

4839.55.55.57.80.550

VVmAnAmAmW

5.5V≥+VBD≥4.5V,IO=100µA

5.5V≥+VBD≥4.5V,IO=100µA

+VBD–0.6

0

5

30

5.5V≥+VBD≥4.5V5.5V≥+VBD≥4.5VVI=+VBDorBDGND

0.65×(+VBD)

–0.3-50

5

+VBD0.4

+VBD+0.3

0.35×(+VBD)

50

VVnApFVVpFpF

(4)(5)CalculatedonthefirstnineharmonicsoftheinputfrequencyCanvary±30%

4

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SPECIFICATIONS

TA=–40°Cto85°C,+VBD=+VA×1.5to+1.65V,Vref=2.5V,fSAMPLE=1MHzfor3V≤+VA≤3.6V,fSAMPLE=900kHzfor3V<+VA≤2.7Vusingexternalclock(unlessotherwisenoted)

PARAMETER

ANALOGINPUT

Full-scaleinputvoltageAbsoluteinputvoltageInputcapacitanceInputleakagecurrent

Inputchannelisolation,ADS8330only

SYSTEMPERFORMANCE

ResolutionNomissingcodes

INL

Integrallinearity

ADS8329IB,ADS8330IB

ADS8329I,ADS8330I

DNL

Differentiallinearity

ADS8329IB,ADS8330IB

ADS8329I,ADS8330IADS8329IB,ADS8330IB

ADS8329I,ADS8330I

Offseterrordrift

EG

GainerrorGainerrordrift

CMRR

CommonmoderejectionratioNoise

PSRRtCONVtSAMPLE1tSAMPLE2

PowersupplyrejectionratioConversiontimeAcquisitiontimeThroughputrateAperturedelayAperturejitterStepresponseOvervoltagerecovery

510100100

ManualtriggerAutotrigger

3

3

1

AtFFFFhoutputcode(3)

SAMPLINGDYNAMICS

18

CCLKCCLKMHznspsnsns

Atdc

VI=0.4Vppat1MHzFSR=2.5V

–0.25

16–1.75–2.5–1–1–0.5–0.8

±1±1.5±0.5±0.8±0.05±0.20.8–0.040.570503378

0.251.752.5120.50.8

PPM/°C%FSRPPM/°CdBµVRMSdBmVLSB(2)

16

BitsBitsLSB(2)

Noongoingconversion,DCInputAtdc

VI=±1.25Vppat50kHz

-1

108101

(1)

TESTCONDITIONS

+IN–(–IN)or(+INx–COM)+IN,+IN0,+IN1–INorCOM

MIN0

AGND–0.2AGND–0.2

TYPMAX+Vref

+VA+0.2AGND+0.2

UNITVVpFnAdB

40451

EOOffseterror(3)

(1)(2)(3)Idealinputspan,doesnotincludegainoroffseterror.LSBmeansleastsignificantbit

Measuredrelativetoanidealfull-scaleinput[+IN–(–IN)]of2.5Vwhen+VA=3V.

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SPECIFICATIONS(continued)

TA=–40°Cto85°C,+VBD=+VA×1.5to+1.65V,Vref=2.5V,fSAMPLE=1MHzfor3V≤+VA≤3.6V,fSAMPLE=900kHzfor3V<+VA≤2.7Vusingexternalclock(unlessotherwisenoted)

PARAMETER

DYNAMICCHARACTERISTICSTHDSNRSINADSFDR

TotalharmonicdistortionSignal-to-noiseratioSignal-to-noise+distortionSpuriousfreedynamicrange-3dBSmallsignalbandwidth

CLOCK

InternalconversionclockfrequencySCLKExternalserialclock

EXTERNALVOLTAGEREFERENCEINPUTVref

InputreferencerangeResistance

(5)

(4)

TESTCONDITIONS

VIN=2.5Vppat10kHzVIN=2.5Vppat100kHzVIN=2.5Vppat10kHzVIN=2.5Vppat100kHzVIN=2.5Vppat10kHzVIN=2.5Vppat100kHzVIN=2.5Vppat10kHzVIN=2.5Vppat100kHz

MINTYP–102–938888.58810494.230

MAXUNIT

dBdBdBdBMHz

23.24230.1

MHzMHz

21

UsedasI/Oclockonly

AsI/Oclockandconversionclock3.6V≥+VA≥2.7VReferenceinput

12.475–0.1

22.3

Vref[REF+–(REF–)](REF–)–AGND

VkΩ

40

DIGITALINPUT/OUTPUT

Logicfamily—CMOS

VIHVILIICiVOHVOLCOCL

High-levelinputvoltageLow-levelinputvoltageInputcurrentInputcapacitanceHigh-leveloutputvoltageLow-leveloutputvoltageOutputcapacitanceLoadcapacitance

Dataformat—straightbinary

POWERSUPPLYREQUIREMENTS

+VBD

Powersupplyvoltage

+VA

fs≤1MHzfs≤900kHz1-MHzSamplerate,3V≤+VA≤3.6V

Supplycurrent

900-kHzSamplerate,2.7V≤+VA≤3VNapmodePDMode

BufferI/OsupplycurrentPowerdissipation

TEMPERATURERANGETA

Operatingfree-airtemperature

–40

85

°C

1MSPS,+VBD=1.8V

+VBD=1.8V,3V≤+VA≤3.6V+VBD=1.8V,2.7V≤+VA≤3V

1.6532.7

5.14.840.2520.0515.513.2

190.450

nAmAmW

+VA

1.5×(+VA)

3.63.66.1

mAVV

(+VA×1.5)V≥+VBD≥1.65V,IO=100µA

(+VA×1.5)V≥+VBD≥1.65V,IO=100µA

+VBD–0.6

0

5

30

(+VA×1.5)V≥+VBD≥1.65V(+VA×1.5)V≥+VBD≥1.65VVI=+VBDorBDGND

0.65×(+VBD)

–0.3-50

5

+VBD0.4

+VBD+0.30.35×(+VBD)

50

VVnApFVVpFpF

(4)(5)CalculatedonthefirstnineharmonicsoftheinputfrequencyCanvary±30%

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(1)(2)

TIMINGCHARACTERISTICS

Allspecificationstypicalat–40°Cto85°C,+VA=+VBD=5V

PARAMETER

fCCLK

Frequency,conversionclock,CCLK,fCCLK=1/2fSCLK

Setuptime,fallingedgeofCStoEOCHoldtime,fallingedgeofCStoEOCPulseduration,CONVSTlowSetuptime,fallingedgeofCStoEOSHoldtime,fallingedgeofCStoEOSSetuptime,risingedgeofCStoEOSHoldtime,risingedgeofCStoEOSSetuptime,fallingedgeofCStoSCLKPulseduration,SCLKlowPulseduration,SCLKhigh

I/OClockonly

I/Oandconversionclock

tc(SCLK)

Cycletime,SCLK

I/OClock,chainmodeI/Oandconversionclock,chainmode

td(SCLKF-SDOINVALID)td(SCLKF-SDOVALID)td(CSF-SDOVALID)tsu(SDI-SCLKF)th(SDI-SCLKF)td(CSR-SDOZ)tsu(lastSCLKF-CSR)td(SDO-CDI)(1)(2)

Delaytime,fallingedgeofSCLKtoSDOinvalid

Delaytime,fallingedgeofSCLKtoSDOvalid

Delaytime,fallingedgeofCStoSDOvalid,SDOMSBoutput

Setuptime,SDItofallingedgeofSCLKHoldtime,SDItofallingedgeofSCLKDelaytime,risingedgeofCS/FStoSDO3-state

Setuptime,lastfallingedgeofSCLKbeforerisingedgeofCS/FSDelaytime,CDIhightoSDOhighindaisychainmode

10-pFLoad,chainmode

10

16

10-pFLoad10-pFLoad10-pFLoad

84

5

ExternalInternal

tsu(CSF-EOC)th(CSF-EOC)twL(CONVST)tsu(CSF-EOS)th(CSF-EOS)tsu(CSR-EOS)th(CSR-EOS)tsu(CSF-SCLK1R)twL(SCLK)twH(SCLK)

MIN0.5211040202020205882023.82023.85

12122000

nsnsnsnsnsnsnsns

2000

ns

tc(SCLK)-5tc(SCLK)-8tc(SCLK)-8

22.9TYP

MAX2124.5

CCLKnsnsnsnsnsnsnsnsnsUNITMHz

Allinputsignalsarespecifiedwithtr=tf=1.5ns(10%to90%ofVDD)andtimedfromavoltagelevelof(VIL+VIH)/2.Seetimingdiagrams.

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TIMINGCHARACTERISTICS

Allspecificationstypicalat–40°Cto85°C,+VA=2.7v,+VBD=1.8V(unlessotherwisenoted)

PARAMETER

External,3V≤+VA≤3.6V

fCCLKtsu(CSF-EOC)th(CSF-EOC)twL(CONVST)tsu(CSF-EOS)th(CSF-EOS)tsu(CSR-EOS)th(CSR-EOS)tsu(CSF-SCLK1R)twL(SCLK)twH(SCLK)

Frequency,conversionclock,CCLK,fCCLK=1/2fSCLK

Setuptime,fallingedgeofCStoEOCHoldtime,fallingedgeofCStoEOCPulseduration,CONVSTlowSetuptime,fallingedgeofCStoEOSHoldtime,fallingedgeofCStoEOSSetuptime,risingedgeofCStoEOSHoldtime,risingedgeofCStoEOSSetuptime,fallingedgeofCStoSCLKPulseduration,SCLKlowPulseduration,SCLKhigh

I/OClockonly

I/Oandconversionclock,3V≤+VA≤3.6VI/Oandconversionclock,2.7V≤+VA<3V

tc(SCLK)

Cycletime,SCLK

I/OClock,chainmodeI/Oandconversionclock,chainmode,

3V≤+VA≤3.6VI/Oandconversionclock,chainmode,

2.7V≤+VA<3V

td(SCLKF-SDOINVALID)td(SCLKF-SDOVALID)td(CSF-SDOVALID)tsu(SDI-SCLKF)th(SDI-SCLKF)td(CSR-SDOZ)tsu(lastSCLKF-CSR)td(SDO-CDI)(1)(2)

Delaytime,fallingedgeofSCLKtoSDOinvalid

Delaytime,fallingedgeofSCLKtoSDOvalid

Delaytime,fallingedgeofCStoSDOvalid,SDOMSBoutput

Setuptime,SDItofallingedgeofSCLKHoldtime,SDItofallingedgeofSCLKDelaytime,risingedgeofCS/FStoSDO3-state

Setuptime,lastfallingedgeofSCLKbeforerisingedgeofCS/FSDelaytime,CDIhightoSDOhighindaisychainmode

10-pFLoad,chainmode

10

23

10-pFLoad10-pFLoad10-pFLoad

84

8

External,2.7V≤+VA≤3VInternal

(1)(2)

MIN0.50.52110402020202058823.823.826.523.823.8

TYPMAX2118.9

UNITMHzCCLKnsnsnsnsnsns

22.323.5

tc(SCLK)-5tc(SCLK)-8tc(SCLK)-8

nsnsns

20002000

ns

2000

26.58

2000

ns2323

nsnsnsnsnsnsns

Allinputsignalsarespecifiedwithtr=tf=1.5ns(10%to90%ofVDD)andtimedfromavoltagelevelof(VIL+VIH)/2.Seetimingdiagrams.

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PINASSIGNMENTS

ADS8329

ADS8330

RSA PACKAGE(TOP VIEW)RSA PACKAGE(TOP VIEW)

AGNDREF−REF−AGND15COM14161514+IN13121110916REF+(REFIN)NCCONVSTEOC/INT/CDI12345678RESERVED+VA+VBDSCLKREF+(REFIN)NCCONVSTEOC/INT/CDI+IN0131211109−IN12345678+IN1+VA+VBDSCLKFS/CSBDGNDFS/CSNC − No internal connection

BDGNDSDOSDOSDISDISubmitDocumentationFeedback

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ADS8329TerminalFunctions

NAMEAGNDBDGNDCONVSTNO.QFN1583

I/O––I

AnaloggroundInterfaceground

Freezessampleandhold,startsconversionwithnextrisingedgeofinternalclock

Statusoutput.IfprogrammedasEOC,thispinislow(default)whenaconversionisin

progress.Ifprogrammedasaninterrupt(INT),thispinislowforapreprogrammeddurationaftertheendofconversionandavaliddataistobeoutput.ThepolarityofEOCorINTisprogrammable.Thispincanalsobeusedasachaindatainputwhenthedeviceisoperatedinchainmode.

FramesyncsignalforTMS320DSPserialinterfaceorchipselectinputforSPIinterfaceslaveselect(SS-).Noninvertinginput

Invertinginput,usuallyconnectedtogroundNoconnection.

Externalreferenceinput.

ConnecttoAGNDthroughindividualvia.ConnecttoAGNDor+VAClockforserialinterfaceSerialdatainSerialdataout

Analogsupply,+2.7Vto+5.5VDC.Interfacesupply

DESCRIPTION

EOC/INT/CDI4O

FS/CS+IN-INNCREF+REF-RESERVEDSCLKSDISDO+VA+VBD

513142116129671110

III–IIIIIO

ADS8330TerminalFunctions

NAMEAGNDBDGNDCOMCONVSTNO.QFN158143

I/O––II

AnaloggroundInterfaceground

Commoninvertinginput,usuallyconnectedtoground

Freezessampleandhold,startsconversionwithnextrisingedgeofinternalclock

Statusoutput.IfprogrammedasEOC,thispinislow(default)whenaconversionisin

progress.Ifprogrammedasaninterrupt(INT),thispinislowforapreprogrammeddurationaftertheendofconversionandavaliddataistobeoutput.ThepolarityofEOCorINTisprogrammable.Thispincanalsobeusedasachaindatainputwhenthedeviceisoperatedinchainmode.

FramesyncsignalforTMS320DSPserialinterfaceorchipselectinputforSPIinterfaceSecondnoninvertinginput.FirstnoninvertinginputNoconnection.

Externalreferenceinput.

ConnecttoAGNDthroughindividualvia.Clockforserialinterface

Serialdatain(conversionstartandresetpossible)Serialdataout

Analogsupply,+2.7Vto+5.5VDC.Interfacesupply

DESCRIPTION

EOC/INT/CDI4O

FS/CS+IN1+IN0NCREF+REF-SCLKSDISDO+VA+VBD

5121321169671110

III–IIIIO

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MANUALTRIGGER󰀀/󰀀READ󰀀While󰀀Sampling

(use󰀀internal󰀀CCLK,󰀀EOC󰀀andINTpolarity󰀀programmed󰀀as󰀀active󰀀low)

CONVSTEOSEOCNthEOStwL(CONVST)NthtCONV=󰀀18󰀀CCLKsEOCEOC

(active󰀀low)tSAMPLE1=󰀀3󰀀CCLKs󰀀minINT(active󰀀low)tSAMPLE1=󰀀3󰀀CCLKs󰀀minth(CSF-EOC)th(CSF-EOS)th(CSR-EOS)tsu(CSF-EOC)th(CSF-EOC)tsu(CSF-EOS)1CS/FSSCLK

1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀16td(CSR-EOS)=󰀀20󰀀ns󰀀minNth1101bSDOSDI

1101bNth−1thREAD󰀀ResultREAD󰀀ResultFigure1.TimingforConversionandAcquisitionCyclesforManualTrigger(Readwhilesampling)

AUTO󰀀TRIGGER󰀀/󰀀READ󰀀While󰀀Sampling

(use󰀀internal󰀀CCLK,󰀀EOC󰀀andINTpolarity󰀀programmed󰀀as󰀀active󰀀low)

CONVST=󰀀1EOSEOCEOSEOCEOS1NthEOC

(active󰀀low)NthtCONV=󰀀18󰀀CCLKsINT(active󰀀low)th(CSF-EOC)tSAMPLE2=󰀀3󰀀CCLKstCONV=󰀀18󰀀CCLKsth(CSF-EOS)tSAMPLE2=󰀀3󰀀CCLKstsu(CSF-EOS)CS/FSSCLKSDOSDI

1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.16N−1thtsu(CSF-EOS)1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.16N−1thth(CSF-EOC)1110b.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.1101b1101bCONFIGUREREAD󰀀ResultREAD󰀀ResultFigure2.TimingforConversionandAcquisitionCyclesforAutotrigger(Readwhilesampling)

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MANUALTRIGGER󰀀/󰀀READ󰀀While󰀀Converting

(use󰀀internal󰀀CCLK,󰀀EOC󰀀andINTpolarity󰀀programmed󰀀as󰀀active󰀀low)

www.ti.com

CONVSTNthtwL(CONVST)NthtCONV=󰀀18󰀀CCLKsN−1thEOCEOSEOSN󰀀+󰀀1thEOC(active󰀀low)tSAMPLE1=󰀀3󰀀CCLKs󰀀minINT(active󰀀low)tsu(CSF-EOS)CS/FStsu(CSF-EOC)SCLK1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.16th(CSF-EOS)tsu(CSR-EOS)th(CSF-EOC)1N󰀀th1101bSDOSDI

1101bN−1thREAD󰀀ResultREAD󰀀ResultFigure3.TimingforConversionandAcquisitionCyclesforManualTrigger(Readwhileconverting)

AUTO󰀀TRIGGER󰀀/󰀀READ󰀀While󰀀Converting

(use󰀀internal󰀀CCLK,󰀀EOC󰀀andINTpolarity󰀀programmed󰀀as󰀀active󰀀low)

CONVST=󰀀1EOSEOCEOSEOCEOC(active󰀀low)N󰀀+󰀀1thtCONV=󰀀18󰀀CCLKsINT(active󰀀low)tsu(CSF-EOS)CS/FSSCLKSDOSDI

th(CSR-EOS)NthtSAMPLE2=󰀀3󰀀CCLKs󰀀mintCONV=󰀀18󰀀CCLKstSAMPLE2=󰀀3󰀀CCLKs󰀀mintsu(CSR-EOS)th(CSF-EOS)th(CSF-EOS)1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀161󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.16N−1󰀀th1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀16N−1󰀀th1101btsu(CSR-EOS)N󰀀th1101b??1110b󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.CONFIGUREREAD󰀀ResultREAD󰀀ResultFigure4.TimingforConversionandAcquisitionCyclesforAutotrigger(Readwhileconverting)

12

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1234567141516SCLKtsu(CSF−SCLK1R)CS/FStc(SCLK)twH(SCLK)tsu(LastSCLK−CSR)twL(SCLK)td(SCLKF−SDOINVALID)td(SCLKF−SDOVALID)MSB−5MSB−6td(CSR−SDOZ)td(CSF−SDOVALID)SDOHi−ZMSBMSB−1MSB−2MSB−3MSB−4LSB+2LSB+1LSBth(SDI−SCLKF)SDIMSBMSB−1MSB−2MSB−3MSB−4MSB−5MSB−6LSB+2LSB+1LSBtsu(SDI−SCLKF)Figure5.DetailedSPITransferTiming

MANUALTRIGGER󰀀/󰀀READ󰀀While󰀀Sampling

(use󰀀internal󰀀CCLKactive󰀀high,󰀀EOC󰀀andINTactive󰀀low,󰀀TAG󰀀enabled,󰀀auto󰀀channel󰀀select)

Nth󰀀CH0CONVSTtwL(CONVST)EOCNthCH1twL(CONVST)Nth󰀀CH1tCONV=󰀀18󰀀CCLKstCONV=󰀀18󰀀CCLKsEOC

(active󰀀low)EOSNth󰀀CH0tSAMPLE1=󰀀3󰀀CCLKs󰀀minINT(active󰀀low)tsu(CSF-EOS)th(CSF-EOC)CS/FSSCLK

Hi−Z

N−1th󰀀CH1

1.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.16

17

1󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀16.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.

17

td(CSR-EOS)=20󰀀ns󰀀MIN

SDOSDI

Nth󰀀CH0

Hi−Z

TAG󰀀=󰀀0TAG󰀀=󰀀11101b1101bREAD󰀀ResultREAD󰀀ResultFigure6.SimplifiedDualChannelTiming

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TYPICALCHARACTERISTICS

At–40°Cto85°C,Vref[REF+–(REF–)]=5Vwhen+VA=+VBD=5VorVref[REF+–(REF–)]=2.5Vwhen+VA=+VBD=3V,fSCLK=42MHz,orVref=2.5when+VA=+VBD=2.7V,fSCLK=37.8MHz,fi=DCforDCcurves,fi=100kHzforACcurveswith5-Vsupplyandfi=10kHzforACcurveswith3-Vsupply(unlessotherwisenoted)

CROSSTALK

vs

FREQUENCY

1101051001DIFFERENTIALNONLINEARITY

vs

FREE-AIRTEMPERATURE

2

INTEGRALNONLINEARITY

vs

FREE-AIRTEMPERATURE

0.81.5

+VA=󰀀5󰀀VCrosstalk󰀀-dBDNL-󰀀LSB0.6+VA=󰀀3󰀀VINL-󰀀LSB959085+VA=󰀀5󰀀V1

+VA=󰀀3󰀀V0.4+VA=󰀀5󰀀V0.2+VA=󰀀3󰀀V0.5

80050

100150

f󰀀-󰀀Frequency󰀀-󰀀kHz

200

0-40-25-10520355065800-40-25TA-󰀀Free-Air󰀀Temperature󰀀-󰀀°C

-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀°C

80Figure7.

DIFFERENTIALNONLINEARITY

vs

EXTERNALCLOCKFREQUENCY

12Figure8.

INTEGRALNONLINEARITY

vs

EXTERNALCLOCKFREQUENCY

+VA=󰀀5󰀀V1

1.51MAX0.5

Figure9.

DIFFERENTIALNONLINEARITY

vs

EXTERNALCLOCKFREQUENCY

+VA=󰀀3󰀀VMAX+VA=󰀀5󰀀VMAX0.5INL-󰀀LSBDNL-󰀀LSB0

MIN-0.5

0-0.5-1-1.5MINDNL-󰀀LSB0.50

MIN-0.5

-10.1

110

External󰀀Clock󰀀Frequency󰀀-󰀀MHz

100

-20.1

101

External󰀀Clock󰀀Frequency󰀀-󰀀MHz

100

-10.1

110

External󰀀Clock󰀀Frequency󰀀-󰀀MHz

100

Figure10.Figure11.Figure12.

14

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TYPICALCHARACTERISTICS(continued)

INTEGRALNONLINEARITY

vs

EXTERNALCLOCKFREQUENCY

21.51

1

OFFSETVOLTAGE

vs

FREE-AIRTEMPERATURE

1

OFFSETVOLTAGE

vs

SUPPLYVOLTAGE

+VA=󰀀3󰀀VMAX0.8

+VA=󰀀5󰀀VINL-󰀀LSB0.50-0.5-1-1.5-20.1

110

External󰀀Clock󰀀Frequency󰀀-󰀀MHz

100

MINOffset󰀀Voltage󰀀-󰀀mVOffset󰀀Voltage󰀀-󰀀mV0.50.6

0+VA=󰀀3󰀀V0.4

-0.5

0.202.7

-1-40-25-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀°C

803.2

3.74.24.7+VA-󰀀Supply󰀀Voltage󰀀-󰀀V

5.2

Figure13.Figure14.Figure15.

POWERSUPPLYREJECTION

RATIOvs

SUPPLYRIPPLEFREQUENCY

PSRR󰀀-󰀀Power󰀀Supply󰀀Rejection󰀀Ratio󰀀-󰀀dB-80GAINERROR

vs

FREE-AIRTEMPERATURE

00.10

GAINERROR

vs

SUPPLYVOLTAGE

-0.02-78Gain󰀀Error󰀀-󰀀%FSR+VA=󰀀5󰀀V-0.04Gain󰀀Error󰀀-󰀀%FSR0.05

-76+VA=󰀀3󰀀V-0.060

-74+VA=󰀀5󰀀V-0.08-0.05

-72+VA=󰀀3󰀀V-700

20

4060f󰀀-󰀀Frequency󰀀-󰀀kHz

80

100

-0.10-40-25-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀°C

80-0.10

2.7

3.23.74.24.75.2

+VA-󰀀Supply󰀀Voltage󰀀-󰀀V

Figure16.Figure17.

SIGNAL-TO-NOISEAND

DISTORTION

vs

INPUTFREQUENCY

SINAD󰀀-󰀀Signal-To-Noise󰀀and󰀀Distortion󰀀-󰀀dB95-90Figure18.

SIGNAL-TO-NOISERATIO

vs

INPUTFREQUENCY

95

TOTALHARMONICDISTORTION

vs

INPUTFREQUENCY

THD󰀀-󰀀Total󰀀Harmonic󰀀Distortion󰀀-󰀀dB+VA=󰀀3󰀀V-95+VA=󰀀5󰀀V-100

SNR󰀀-󰀀Signal-To-Noise󰀀Ratio󰀀-󰀀dB93+VA=󰀀5󰀀V93+VA=󰀀5󰀀V9191+VA=󰀀3󰀀V+VA=󰀀3󰀀V87

-10587850

20406080fi-󰀀Input󰀀Frequency󰀀-󰀀kHz

100

85-110020406080fi-InputFrequency-kHz

1000

20406080fi-InputFrequency-kHz

100

Figure19.Figure20.

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TYPICALCHARACTERISTICS(continued)

SPURIOUSFREEDYNAMICRANGE

vs

INPUTFREQUENCY

SFDR󰀀-󰀀Spurious󰀀Free󰀀Dynamic󰀀Range󰀀-󰀀dB11010010810610410210096949290700

20406080fi-InputFrequency-kHz

100

0

1

23

Full󰀀Scale󰀀Range󰀀-󰀀V

4

5

+VA=󰀀3󰀀V+VA=󰀀5󰀀VSIGNAL-TO-NOISERATIO

vs

FULLSCALERANGE

fi=󰀀10󰀀kHz9590858075SIGNAL-TO-NOISEAND

DISTORTION

vs

FULLSCALERANGE

SINAD󰀀-󰀀Signal-To-Noise󰀀and󰀀Distortion󰀀-󰀀dB100fi=󰀀10󰀀kHz95908580757001

32

Full󰀀Scale󰀀Range󰀀-󰀀V

4

5

SNR󰀀-󰀀Signal-To-Noise󰀀Ratio󰀀-󰀀dB+VA=󰀀3󰀀V+VA=󰀀5󰀀V+VA=󰀀3󰀀V+VA=󰀀5󰀀VFigure22.

TOTALHARMONICDISTORTION

vs

FULLSCALERANGE

THD󰀀-󰀀Total󰀀Harmonic󰀀Distortion󰀀-󰀀dBfi=󰀀10󰀀kHz-85-90-95

+VA=󰀀5󰀀V-100-105-110

+VA=󰀀3󰀀VFigure23.

SPURIOUSFREEDYNAMICRANGE

vs

FULLSCALERANGE

SFDR󰀀-󰀀Spurious󰀀Free󰀀Dynamic󰀀Range󰀀-󰀀dB110105100959085800-90Figure24.

TOTALHARMONICDISTORTION

vs

FREE-AIRTEMPERATURE

THD󰀀-󰀀Total󰀀Harmonic󰀀Distortion󰀀-󰀀dB-80

fi=󰀀10󰀀kHz+VA=󰀀3󰀀V+VA=󰀀5󰀀V+VA=󰀀5󰀀V-95-100+VA=󰀀3󰀀V-1050123Full󰀀Scale󰀀Range󰀀-󰀀V

45123Full󰀀Scale󰀀Range󰀀-󰀀V

45

-110-40-25-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀°C

80Figure25.Figure26.Figure27.

SIGNAL-TO-NOISEAND

DISTORTION

vs

FREE-AIRTEMPERATURE

SINAD󰀀-󰀀Signal-To-Noise󰀀and󰀀Distortion󰀀-󰀀dB95SPURIOUSFREEDYNAMICRANGE

vs

FREE-AIRTEMPERATURE

SFDR󰀀-󰀀Spurious󰀀Free󰀀Dynamic󰀀Range󰀀-󰀀dB11095SIGNAL-TO-NOISERATIO

vs

FREE-AIRTEMPERATURE

SNR󰀀-󰀀Signal-To-Noise󰀀Ratio󰀀-󰀀dB93105+VA=󰀀3󰀀V+VA=󰀀5󰀀V939191100+VA=󰀀5󰀀V+VA=󰀀3󰀀V95+VA=󰀀5󰀀V+VA=󰀀3󰀀V878790-40

-25

-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀°C

80

85-40-25-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀ºC

8085-40

-25-1052035506580

TA-󰀀Free-Air󰀀Temperature󰀀-󰀀ºC

Figure28.

16

Figure29.

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TYPICALCHARACTERISTICS(continued)

EFFECTIVENUMBEROFBITS

vs

FREE-AIRTEMPERATURE

1624

INTERNALCLOCKFREQUENCY

vs

SUPPLYVOLTAGE

24

INTERNALCLOCKFREQUENCY

vs

FREE-AIRTEMPERATURE

ENOB󰀀-󰀀Effective󰀀Number󰀀of󰀀Bits󰀀-󰀀Bits15.50Internal󰀀Clock󰀀Frequency󰀀-󰀀MHz2322.52221.5212.7

Internal󰀀Clock󰀀Frequency󰀀-󰀀MHz3.2

3.74.24.7+VA-󰀀Supply󰀀Voltage󰀀-󰀀V

5.2

23.523.5

2322.52221.5

21

-40-25-10520355065

TA-󰀀Free-Air󰀀Temperature󰀀-󰀀ºC

+VA=󰀀5󰀀V15+VA=󰀀3󰀀V14.5014-40-25-105203550658080

TA-󰀀Free-Air󰀀Temperature󰀀-󰀀ºC

Figure31.

ANALOGSUPPLYCURRENT

vs

SUPPLYVOLTAGE

4007.5fs=󰀀1󰀀MSPSNAPModeFigure32.

ANALOGSUPPLYCURRENT

vs

SUPPLYVOLTAGE

10PD󰀀ModeFigure33.

ANALOGSUPPLYCURRENT

vs

SUPPLYVOLTAGE

Analog󰀀Supply󰀀Current󰀀-󰀀mA7.06.56.05.55.04.52.7

Analog󰀀Supply󰀀Current󰀀-mAAnalog󰀀Supply󰀀Current󰀀-󰀀nA36083206280424023.2

3.74.24.75.2+VA-󰀀Supply󰀀Voltage󰀀-󰀀V

2002.7

3.2

3.74.24.7+VA-󰀀Supply󰀀Voltage󰀀-󰀀V

5.2

02.7

3.2

3.74.24.7+VA-󰀀Supply󰀀Voltage󰀀-󰀀V

5.2

Figure34.

ANALOGSUPPLYCURRENT

vs

SAMPLERATE

5007

Auto󰀀NAPFigure35.

ANALOGSUPPLYCURRENT

vs

SAMPLERATE

PD󰀀ModeAnalog󰀀Supply󰀀Current󰀀-󰀀mAAnalog󰀀Supply󰀀Current󰀀-mA400

7.576.565.5.-40

-25

Figure36.

ANALOGSUPPLYCURRENT

vs

FREE-AIRTEMPERATURE

fs=󰀀1󰀀MSPSAnalog󰀀Supply󰀀Current󰀀-󰀀mA63210

+VA=󰀀5󰀀V+VA=󰀀5󰀀V300+VA=󰀀3󰀀V+VA=󰀀5󰀀V200

+VA=󰀀3󰀀V100+VA=󰀀3󰀀V1

10100Sample󰀀Rate󰀀-󰀀kHz

100001591317

Sample󰀀Rate󰀀-󰀀kHz

-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀ºC

80

Figure37.Figure38.Figure39.

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TYPICALCHARACTERISTICS(continued)

ANALOGSUPPLYCURRENT

vs

FREE-AIRTEMPERATURE

0.4

NAPModeAnalog󰀀Supply󰀀Current󰀀-󰀀mA0.36

0.32

+VA=󰀀5󰀀V0.28+VA=󰀀3󰀀V0.240.2-40-25-10520355065TA-󰀀Free-Air󰀀Temperature󰀀-󰀀ºC

80Figure40.

INL

1.751.51.00.50-0.5-1.0-1.5-1.750

10000

20000

30000

Code

40000

50000

60000

+VA=󰀀5󰀀VINL-󰀀BitsFigure41.

DNL

1

+VA=󰀀5󰀀V0.5

DNL-󰀀Bits0

-0.5-1

0100002000030000Code

400005000060000Figure42.

18

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TYPICALCHARACTERISTICS(continued)

INL

1.751.51.00.50-0.5-1.0-1.5-1.75

0

10000

20000

30000

Code

40000

50000

60000

+VA=󰀀3󰀀V

INL-󰀀BitsFigure43.

DNL

1+VA=󰀀3󰀀V0.5DNL-󰀀Bits0

-0.5-10

10000

20000

30000

Code

40000

50000

60000

Figure44.

FFT

0-20-405󰀀kHz󰀀Input,+VA=󰀀3󰀀V,fs=󰀀1󰀀MSPS,Vref=󰀀2.5󰀀VAmplitude󰀀-󰀀dB-60-80-100-120-140-1600

100

200

f󰀀-󰀀Frequency󰀀-󰀀kHz

300

400

500

Figure45.

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TYPICALCHARACTERISTICS(continued)

0-20-40

10󰀀kHz󰀀Input,+VA=󰀀3󰀀V,fs=󰀀1󰀀MSPS,Vref=󰀀2.5󰀀VFFT

Amplitude󰀀-󰀀dB-60-80-100-120-140-160

0

100

200

f󰀀-󰀀Frequency󰀀-󰀀kHz

300

400

500

Figure46.

0-20-40FFT

100󰀀kHz󰀀Input,+VA=󰀀3󰀀V,fs=󰀀1󰀀MSPS,Vref=󰀀2.5󰀀VAmplitude󰀀-󰀀dB-60-80-100-120-140-1600100200f󰀀-󰀀Frequency󰀀-󰀀kHz

300400500Figure47.

0-20FFT

5󰀀kHz󰀀Input,+VA=󰀀5󰀀V,fs=󰀀1󰀀MSPS,Vref=󰀀5󰀀VAmplitude󰀀-󰀀dB-40-60-80-100-120-140-1600

100

200

f󰀀-󰀀Frequency󰀀-󰀀kHz

300

400500

Figure48.

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TYPICALCHARACTERISTICS(continued)

200-20FFT

10󰀀kHz󰀀Input,+VA=󰀀5󰀀V,fs=󰀀1󰀀MSPS,Vref=󰀀5󰀀VAmplitude󰀀-󰀀dB-40-60-80-100-120-140-1600

100

200

f󰀀-󰀀Frequency󰀀-󰀀kHz

300

400

500

Figure49.

FFT

0-20-40100󰀀kHz󰀀Input,+VA=󰀀5󰀀V,fs=󰀀1󰀀MSPS,Vref=󰀀5󰀀VAmplitude󰀀-󰀀dB-60-80-100-120-140-1600

100

200

300

400

500

f󰀀-󰀀Frequency󰀀-󰀀kHz

Figure50.

THEORYOFOPERATION

TheADS8329/30isahigh-speed,lowpower,successiveapproximationregister(SAR)analog-to-digitalconverter(ADC)thatusesanexternalreference.Thearchitectureisbasedonchargeredistribution,whichinherentlyincludesasample/holdfunction.

TheADS8329/30hasaninternalclockthatisusedtoruntheconversionbutcanalsobeprogrammedtoruntheconversionbasedontheexternalserialclock,SCLK.

TheADS8329hasoneanaloginput.Theanaloginputisprovidedtotwoinputpins:+INand–IN.Whenaconversionisinitiated,thedifferentialinputonthesepinsissampledontheinternalcapacitorarray.Whileaconversionisinprogress,both+INand–INinputsaredisconnectedfromanyinternalfunction.

TheADS8330hastwoinputs.Bothinputssharethesamecommonpin-COM.Thenegativeinputisthesameasthe-INpinfortheADS8329.TheADS8330canbeprogrammedtoselectachannelmanuallyorcanbeprogrammedintotheautochannelselectmodetosweepbetweenchannel0and1automatically.

ANALOGINPUT

Whentheconverterentersholdmode,thevoltagedifferencebetweenthe+INand–INinputsiscapturedontheinternalcapacitorarray.Thevoltageonthe–INinputislimitedbetweenAGND–0.2VandAGND+0.2V,allowingtheinputtorejectsmallsignalswhicharecommontoboththe+INand–INinputs.The+INinputhasarangeof–0.2VtoVref+0.2V.Theinputspan[+IN–(–IN)]islimitedto0VtoVref.

The(peak)inputcurrentthroughtheanaloginputsdependsuponanumberoffactors:samplerate,input

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THEORYOFOPERATION(continued)

voltage,andsourceimpedance.ThecurrentintotheADS8329/30chargestheinternalcapacitorarrayduringthesampleperiod.Afterthiscapacitancehasbeenfullycharged,thereisnofurtherinputcurrent.Thesourceoftheanaloginputvoltagemustbeabletochargetheinputcapacitance(45pF)toa16-bitsettlinglevelwithintheminimumacquisitiontime(120ns).Whentheconvertergoesintoholdmode,theinputimpedanceisgreaterthan1GΩ.

Caremustbetakenregardingtheabsoluteanaloginputvoltage.Tomaintainlinearityoftheconverter,the+INand–INinputsandthespan[+IN–(–IN)]shouldbewithinthelimitsspecified.Outsideoftheseranges,converterlinearitymaynotmeetspecifications.Tominimizenoise,lowbandwidthinputsignalswithlow-passfiltersshouldbeused.Careshouldbetakentoensurethattheoutputimpedanceofthesourcesdrivingthe+INand–INinputsarematched.Ifthisisnotobserved,thetwoinputscouldhavedifferentsettlingtimes.Thismayresultinanoffseterror,gainerror,andlinearityerrorwhichchangewithtemperatureandinputvoltage.

Device in Hold Mode150 W4 pF4 pF−IN

AGND+VA150 W40 pFAGND40 pF+IN

Figure51.InputEquivalentCircuit

DriverAmplifierChoice

Theanaloginputtotheconverterneedstobedrivenwithalownoise,op-ampliketheTHS4031orOPA365.AnRCfilterisrecommendedattheinputpinstolow-passfilterthenoisefromthesource.Tworesistorsof20Ωandacapacitorof470pFarerecommended.Theinputtotheconverterisaunipolarinputvoltageintherange0VtoVref.Theminimum-3dBbandwidthofthedrivingoperationalamplifiercanbecalculatedto:

f3db=(ln(2)×(n+1))/(2π×tACQ)

wherenisequalto16,theresolutionoftheADC(inthecaseoftheADS8329/30).WhentACQ=120ns(minimumacquisitiontime),theminimumbandwidthofthedrivingamplifieris15.6MHz.Thebandwidthcanberelaxediftheacquisitiontimeisincreasedbytheapplication.TheOPA365,OPA827,orTHS4031fromTexasInstrumentsarerecommended.TheTHS4031usedinthesourcefollowerconfigurationtodrivetheconverterisshowninthetypicalinputdriveconfiguration,Figure52.

BipolartoUnipolarDriver

Insystemswheretheinputisbipolar,theTHS4031canbeusedintheinvertingconfigurationwithanadditionalDCbiasappliedtoits+inputsoastokeeptheinputtotheADS8329/30withinitsratedoperatingvoltagerange.ThisconfigurationisalsorecommendedwhentheADS8329/30isusedinsignalprocessingapplicationswheregoodSNRandTHDperformanceisrequired.TheDCbiascanbederivedfromtheREF3225ortheREF3240referencevoltageICs.TheinputconfigurationshowninFigure53iscapableofdeliveringbetterthan91dBSNRand–96dBTHDataninputfrequencyof10kHz.Incasebandpassfiltersareusedtofiltertheinput,careshouldbetakentoensurethatthesignalswingattheinputofthebandpassfilterissmallsoastokeepthedistortionintroducedbythefilterminimal.Insuchcases,thegainofthecircuitshowninFigure53canbeincreasedtokeeptheinputtotheADS8329/30largetokeeptheSNRofthesystemhigh.Notethatthegainofthesystemfromthe+inputtotheoutputoftheTHS4031insuchaconfigurationisafunctionofthegainoftheACsignal.AresistordividercanbeusedtoscaletheoutputoftheREF3225orREF3240toreducethevoltageattheDCinputtoTHS4031tokeepthevoltageattheinputoftheconverterwithinitsratedoperatingrange.

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THEORYOFOPERATION(continued)

InputSignal(0 V to 4 V)THS403120 W470 pF50 W−IN/COM20 WADS8329/30+VA+IN/(+IN1 or +IN0)5 VFigure52.UnipolarInputDriveConfiguration

5 V+VATHS403120 W470 pFInputSignal(−2V to 2 V)600 W−IN/COM20 W+IN/(+IN1 or +IN0)ADS83291 V DC600 WFigure53.BipolarInputDriveConfiguration

REFERENCE

TheADS8329/30canoperatewithanexternalreferencewitharangefrom0.3Vto5V.Aclean,lownoise,well-decoupledreferencevoltageonthispinisrequiredtoensuregoodperformanceoftheconverter.Alownoiseband-gapreferenceliketheREF3240canbeusedtodrivethispin.A22-µFceramicdecouplingcapacitorisrequiredbetweentheREF+andREF-pinsoftheconverter.Thesecapacitorsshouldbeplacedascloseaspossibletothepinsofthedevice.TheREF-shouldbeconnectedtoitsownviatotheanaloggroundplanewiththeshortestpossibledistance.

CONVERTEROPERATION

TheADS8329/30hasanoscillatorthatisusedasaninternalclockwhichcontrolstheconversionrate.Thefrequencyofthisclockis21MHzminimum.TheoscillatorisalwaysonunlessthedeviceisinthedeeppowerdownstateorthedeviceisprogrammedforusingSCLKastheconversionclock(CCLK).Theminimumacquisition(sampling)timetakes3CCLKs(thisisequivalentto120nsat24.5MHz)andtheconversiontimetakes18conversionclocks(CCLK)(~780ns)tocompleteoneconversion.

Theconversioncanalsobeprogrammedtorunbasedontheexternalserialclock,SCLK,ifissodesired.Thisallowsasystemdesignertoachievesystemsynchronization.TheserialclockSCLK,isfirstreducedto1/2ofitsfrequencybeforeitisusedastheconversionclock(CCLK).Forexample,witha42-MHzSCLKthisprovidesa21-MHzclockforconversions.IfitisdesiredtostartaconversionataspecificrisingedgeoftheSCLKwhentheexternalSCLKisprogrammedasthesourceoftheconversionclock(CCLK)(andmanualstartofconversionisselected),thesetuptimebetweenCONVSTandthatrisingSCLKedgeshouldbeobserved.Thisensurestheconversioniscompletein18CCLKs(or36SCLKs).Theminimumsetuptimeis20nstoensuresynchronizationbetweenCONVSTandSCLK.InmanycasestheconversioncanstartoneSCLKperiod(orCCLK)laterwhichresultsina19CCLK(or37SCLK)conversion.The20nssetuptimeisnotrequiredoncesynchronizationisrelaxed.

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THEORYOFOPERATION(continued)

ThedutycycleofSCLKisnotcriticalaslongasitmeetstheminimumhighandlowtimerequirementsof8ns.SincetheADS8329/30isdesignedforhigh-speedapplications,ahigherserialclock(SCLK)mustbesuppliedtobeabletosustainthehighthroughputwiththeserialinterfaceandsotheclockperiodofSCLKmustbeatmost1µs(whenusedasconversionclock(CCLK).Theminimumclockfrequencyisalsogovernedbytheparasiticleakageofthecapacitivedigital-to-analog(CDAC)capacitorsinternaltotheADS8329/30.

CFR_D10Conversion Clock(CCLK)= 1OSCSPI SerialClock (SCLK)= 0Divider1/2Figure.ConverterClock

ManualChannelSelectMode

Theconversioncyclestartswithselectinganacquisitionchannelbywritingachannelnumbertothecommandregister(CMR).Thiscycletimecanbeasshortas4serialclocks(SCLK).AutoChannelSelectMode

Channelselectioncanalsobedoneautomaticallyifautochannelselectmodeisenabled.Thisisthedefaultchannelselectmode.Thedualchannelconverter,ADS8330,hasabuilt-in2-to-1MUX.Ifthedeviceisprogrammedforautochannelselectmodethensignalsfromchannel0andchannel1areacquiredwithafixedorder.Channel0isaccessedfirstinthenextcycleafterthecommandcyclethatconfiguredCFR_D11to1forautochannelselectmode.ThisautomaticaccessstopsthecycleafterthecommandcyclethatsetsCFR_D11to0.

StartofaConversion

Theendofacquisitionorsamplinginstance(EOS)isthesameasthestartofaconversion.ThisisinitiatedbybringingtheCONVSTpinlowforaminimumof40ns.Aftertheminimumrequirementhasbeenmet,theCONVSTpincanbebroughthigh.CONVSTactsindependentofFS/CSsoitispossibletouseonecommonCONVSTforapplicationsrequiringsimultaneoussample/holdwithmultipleconverters.TheADS8329/30switchesfromsampletoholdmodeonthefallingedgeoftheCONVSTsignal.TheADS8329/30requires18conversionclock(CCLK)edgestocompleteaconversion.Theconversiontimeisequivalentto1500nswitha12-MHzinternalclock.TheminimumtimebetweentwoconsecutiveCONVSTsignalsis21CCLKs.

AconversioncanalsobeinitiatedwithoutusingCONVSTifitissoprogrammed(CFR_D9=0).Whentheconverterisconfiguredasautotrigger,thenextconversionisautomaticallystarted3conversionclocks(CCLK)aftertheendofaconversion.These3conversionclocks(CCLK)areusedastheacquisitiontime.Inthiscasethetimetocompleteoneacquisitionandconversioncycleis21CCLKs.

Table1.DifferentTypesofConversion

MODE

SELECTCHANNELAutoChannelSelect(1)

AutomaticNoneedtowritechannelnumbertotheCMR.Useinternalsequencerforthe

ADS8330.Manual(1)

ManualChannelSelect

WritethechannelnumbertotheCMR.

STARTCONVERSION

AutoTrigger

StartaconversionbasedontheconversionclockCCLK.

ManualTrigger

StartaconversionwithCONVST.AutochannelselectshouldbeusedwithautotriggerandalsowiththeTAGbitenabled.

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StatusOutputEOC/INTWhenthestatuspinisprogrammedasEOCandthepolarityissetasactivelow,thepinworksinthefollowingmanner:TheEOCoutputgoesLOWimmediatelyfollowingCONVSTgoingLOWwhenmanualtriggerisprogrammed.EOCstaysLOWthroughouttheconversionprocessandreturnstoHIGHwhentheconversionhasended.TheEOCoutputgoeslowfor3conversionclocks(CCLK)afterthepreviousrisingedgeofEOC,ifautotriggerisprogrammed.

Thisstatuspinisprogrammable.ItcanbeusedasanEOCoutput(CFR_D[7:6]=1,1)wherethelowtimeisequaltotheconversiontime.ThisstatuspincanbeusedasINT.(CFR_D[7:6]=1,0)whichissetLOWattheendofaconversionisbroughttoHIGH(cleared)bythenextreadcycle.Thepolarityofthispin,usedaseitherfunction(EOCorINT),isprogrammablethroughCFR_D7.Power-DownModes

TheADS8329/30hasacomprehensivebuilt-inpower-downfeature.Therearethreepower-downmodes:Deeppower-downmode,Nappower-downmode,andautonappower-downmode.Allthreepower-downmodesareenabledbysettingtherelatedCFRbits.Thefirsttwopower-downmodesareactivatedwhenenabled.Awakeupcommand,1011b,canresumedeviceoperationfromapower-downmode.Autonappower-downmodeworksslightlydifferent.Whentheconverterisenabledinautonappower-downmode,anendofconversioninstance(EOC)putsthedeviceintoautonappowerdown.Thebeginningofsamplingresumesoperationoftheconverter.Thecontentsoftheconfigurationregisterisnotaffectedbyanyofthepower-downmodes.Anyongoingconversionwhennapordeeppowerdownisactivatedisaborted.

100

+VA − Supply Current − mA10

1

0.120

1002020020Settling Time − ns

3002040020

Figure55.TypicalAnalogSupplyCurrentDropvsTimeAfterPowerdown

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DeepPower-DownMode

Deeppower-downmodecanbeactivatedbywritingtoconfigurationregisterbitCFR_D2.Whenthedeviceisindeeppower-downmode,allblocksexcepttheinterfaceareinpowerdown.TheexternalSCLKisblockedtotheanalogblock.Theanalogblocksnolongerhavebiascurrentsandtheinternaloscillatoristurnedoff.Inthismode,powerdissipationfallsfrom5mAto1µAin2µs.Thewake-uptimeafterapowerdownis1µs.WhenbitD2intheconfigurationregisterissetto0,thedeviceisindeeppowerdown.Settingthisbitto1orsendingawake-upcommandcanresumetheconverterfromthedeeppower-downstate.NapMode

InnapmodetheADS8329/230turnsoffbiasingofthecomparatorandthemid-voltbuffer.Inthismodepowerdissipationfallsfrom7mAinnormalmodetoabout0.3mAin200nsaftertheconfigurationcycle.Thewake-up(resume)timefromnappower-downmodeis3CCLKs(120nswitha24.5-MHzconversionclock).AssoonastheCFR_D3bitinthecontrolregisterissetto0,thedevicegoesintonappower-downmode,regardlessoftheconversionstate.Settingthisbitto1orsendingawake-upcommandcanresumetheconverterfromthenappower-downstate.AutoNapMode

Autonapmodeisalmostidenticaltonapmode.Theonlydifferenceisthetimewhenthedeviceisactuallypowereddownandthemethodtowakeupthedevice.ConfigurationregisterbitD4isonlyusedtoenable/disableautonapmode.Ifautonapmodeisenabled,thedeviceturnsoffbiasingaftertheconversionhasfinished,whichmeanstheendofconversionactivatesautonappowerdownmode.Powerdissipationfallsfrom7mAinnormalmodetoabout0.3mAin200ns.ACONVSTresumesthedeviceandturnsbiasingonagainin3CCLKs(120nswitha24.5-MHzconversionclock).ThedevicecanalsobewokenupbydisablingautonapmodewhenbitD4oftheconfigurationregisterissetto1.Anychannelselectcommand0XXXb,wakeupcommandorthesetdefaultmodecommand1111bcanalsowakeupthedevicefromautonappowerdown.

NOTE:

1.Thiswake-upcommandistheword1011binthecommandword.Thiscommandsets

bitsD2andD3to1intheconfigurationregisterbutnotD4.Butawake-upcommanddoesremovethedevicefromeitheroneofthesepower-downstates,deep/nap/autonappowerdown.2.Wake-uptimeisdefinedasthetimebetweenwhenthehostprocessortriestowakeup

theconverterandwhenaconvertstartcanoccur.

Table2.Power-DownModeComparisons

TYPEOFPOWERDOWNNormaloperationDeeppowerdownNappowerdown

POWERCONSUMPTION7mA/5.1mA7nA/1nA0.3mA/0.2mA

SettingCFRSettingCFREOC(endofconversion)

100µs200µs

Wokenupbycommand1011b

Wokenupbycommand1011btoachieve6.6mAsince(1.3+12)/2=6.6

WokenupbyCONVST,anychannelselect

command,defaultcommand1111b,orwakeupcommand1011b.

1µs3CCLKs

SetCFRSetCFR

ACTIVATEDBY

ACTIVATIONTIME

RESUMEPOWERBY

RESUMETIME

ENABLE

Autonappowerdown200µs3CCLKsSetCFR

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NEOSEOCConverterStateEOSN+1EOCN+1 −th ConversionN+1EOCEOSEOCN+1 −th Conversion=18 CCLKActivationCONVSTConverterStateN −th ConversionN+1 −th SamplingRead While Converting20 ns MINCS(For Read Result)1 CCLK MINRead N−1 −th ResultRead While Sampling0 ns MIN20 ns MINCS(For Read Result)Read N −th ResultFigure56.ReadWhileConvertingvsReadWhileSampling(Manualtrigger)

Manual TriggerCONVSTEOSConverter

State

ResumeN −th Sampling>=3CCLKN −th Conversion=18 CCLKNActivationResumeN+1 −th Sampling>=3CCLK20 ns MINRead While ConvertingCS1 CCLK MINRead N−1 −thResult20 ns MINRead N −thResult20 ns MINRead While SamplingRead N−1 −thCSResult20 ns MIN20 ns MIN0 ns MINRead N −thResult20 ns MIN20 ns MIN20 ns MINFigure57.ReadWhileConvertingvsReadWhileSamplingwithDeeporNapPowerdown

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40 ns MINNN+1www.ti.com

Manual Trigger Case 1CONVSTEOC(programmedActive Low)EOSEOCEOSConverterStateResumeN −th Sampling>=3CCLKN −th Conversion=18 CCLK6 CCLKsPOWERDOWNResumeN+1 −th Sampling>=3CCLKN+1 −th Conversion=18 CCLK6 CCLKsEOCPOWERDOWN20 ns MINRead N −thResult20 ns MIN1 CCLK MIN20 ns MINEOCN+1 −th Conversion=18 CCLKPOWERDOWN20 ns MINRead N −thResult20 ns MIN20 ns MIN20 ns MINRead While Converting20 ns MINCSRead N−1 −thResult20 ns MINRead While Sampling1 CCLK MIN0 ns MINCSRead N−1 −thResult20 ns MINManual Trigger Case 2 (wake up by CONVST)CONVSTEOC(programmedActive Low)NN+140 ns MINRead N −thResultEOSConverterStateEOCResumeN −th Sampling>=3CCLKN −th Conversion=18 CCLKPOWERDOWNResumeN+1 −th Sampling>=3CCLKRead While Converting20 ns MINCSRead N−1 −thResultRead While Sampling20 ns MIN20 ns MIN0 ns MINRead N −thResult20 ns MINCSRead N−1 −thResultFigure58.ReadWhileConvertingvsReadWhileSamplingwithAutoNapPowerdown

TotalAcquisition+ConversionCycleTime:Automatic:Manual:

Manual+nappowerdown:Manual+autonappowerdown:Manual+autonappowerdown:

28

=21CCLKs≥21CCLKs

≥4SCLK+3CCLK+3CCLK+18CCLK+16SCLK

≥4SCLK+3CCLK+3CCLK+18CCLK+16SCLK(usewakeuptoresume)≥1CCLK+3CCLK+3CCLK+18CCLK+16SCLK(useCONVSTtoresume)

Manual+deeppowerdown:≥4SCLK+100µs+3CCLK+18CCLK+16SCLK+1µs

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DIGITALINTERFACE

TheserialinterfaceiscompatiblewithMotorolaSPI.Theserialclockisdesignedtoaccommodatethelatesthigh-speedprocessorswithanSCLKupto50MHz.EachcycleisstartedwiththefallingedgeofFS/CS.TheinternaldataregistercontentwhichismadeavailabletotheoutputregisterattheEOCpresentedontheSDOoutputpinatthefallingedgeofFS/CS.ThisistheMSB.OutputdataarechangedatthefallingedgeofSCLKsothatthehostprocessorcanreaditatthenextrisingedge.SerialdatainputislatchedatthefallingedgeofSCLK.

ThecompleteserialI/OcyclestartswiththefirstrisingedgeofSCLKafterthefallingedgeofFS/CSandends16(seeNOTE)fallingedgesofSCLKlater.Theserialinterfaceisveryflexible.ItworkswithbothCPOL=0orCPOL=1.Theinterfaceignoresdataifafallingedgearrivesbeforethefirstrisingedge.ThismeansthefallingedgeofFS/CSmayfallwhileSCLKishigh.ThesamerelaxationappliestotherisingedgeofFS/CSwhereSCLKmaybehighorlowaslongasthelastSCLKfallingedgehappensbeforetherisingedgeofFS/CS.NOTE:

Therearecaseswhereacycleis4SCLKsorupto24SCLKsdependingonthereadmodecombination.SeeTable3fordetails.

InternalRegister

Theinternalregisterconsistsoftwoparts,4bitsforthecommandregister(CMR)and12bitsforconfigurationdataregister(CFR).

Table3.CommandSetDefinedbyCommandRegister(CMR)(1)

D[15:12]0000b0001b0010b0011b0100b0101b0110b0111b1000b1001b1010b1011b1100b1101b11101111b(1)(2)

HEX0h1h2h3h4h5h6h7h8h9hAhBhChDhEhFh

COMMAND

Selectanaloginputchannel0(2)Selectanaloginputchannel1(2)ReservedReservedReservedReservedReservedReservedReservedReservedReservedWakeupReadCFRReaddataWriteCFR

Defaultmode(loadCFRwithdefaultvalue)

D[11:0]Don'tcareDon'tcareReservedReservedReservedReservedReservedReservedReservedReservedReservedDon'tcareDon'tcareDon'tcareCFRValueDon'tcare

WAKEUPFROMAUTONAP

YYYYYYYY–––Y–––Y

MINIMUMSCLKsREQUIRED

44444444–––416161

R/W–––––––––––WRRWW

WhenSDOisnotin3-state(FS/CSlowandSCLKrunning),thebitsfromSDOarealwayspart(dependingonhowmanySCLKsaresupplied)ofthepreviousconversionresult.

ThesetwocommandsapplytotheADS8330only.

WRITINGTOTHECONVERTER

Therearetwodifferenttypesofwritestotheregister,a4-bitwritetotheCMRandafull16-bitwritetotheCMRplusCFR.ThecommandsetislistedinTable3.Asimplecommandrequiresonly4SCLKsandthewritetakeseffectatthe4thfallingedgeofSCLK.A16-bitwriteorreadtakesatleast16SCLKs(seeTable5forexceptionsthatrequiremorethan16SCLKs).

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ConfiguringtheConverterandDefaultMode

Theconvertercanbeconfiguringwithcommand1110b(writetotheCFR)orcommand1111b(defaultmode).AwritetotheCFRrequiresa4-bitcommandfollowedby12-bitsofdata.A4-bitcommandtakeseffectatthe4thfallingedgeofSCLK.ACFRwritetakeseffectatthe16thfallingedgeofSCLK.

AdefaultmodecommandcanbeachievedbysimplytyingSDIto+VBD.Assoonasthechipisselectedatleastfour1sareclockedinbySCLK.ThedefaultvalueoftheCFRisloadedintotheCFRatthe4thfallingedgeofSCLK.

CFRdefaultvaluesareall1s(exceptforCFR_D1,thisbitisignoredbytheADS8329andisalwaysreadasa0).ThesamedefaultvaluesapplyfortheCFRafterapower-onreset(POR)andSWreset.

READINGTHECONFIGURATIONREGISTER

ThehostprocessorcanreadbackthevalueprogrammedintheCFRbyissuingcommand1100b.ThetimingissimilartoreadingaconversionresultexceptCONVSTisnotusedandthereisnoactivityontheEOC/INTpin.TheCFRvaluereadbackcontainsthefirstfourMSBsofconversiondataplusvalid12-bitCFRcontents.

Table4.ConfigurationRegister(CFR)Map

SDIBITCFR-D[11-0]

Channelselectmode

D11Default=1

0:Manualchannelselectenabled.Usechannelselectcommandstoaccessadifferentchannel.

Conversionclock(CCLK)sourceselect0:Conversionclock(CCLK)=SCLK/2

0:Autotriggerautomaticallystarts(4internalclocksafterEOCinactive)Don'tcare

Pin10polarityselectwhenusedasanoutput(EOC/INT)0:EOCActivehigh/INTactivehigh

Pin10functionselectwhenusedasanoutput(EOC/INT)0:PinusedasINTPin10I/Oselectforchainmodeoperation

0:Pin10isusedasCDIinput(chainmodeenabled)0:Autonappowerdownenabled(notactivated)0:Enable/activatedeviceinnappowerdown

Deeppowerdown.Thisbitissetto1automaticallybywake-upcommand.0:Enable/activatedeviceindeeppowerdown

TAGbitenable.ThisbitisignoredbytheADS8329andisalwayread0.0:TAGbitdisabled.Reset

0:Systemreset

1:Normaloperation

1:TAGbitoutputenabled.TAGbitappearsatthe17thSCLK.1:Removedevicefromdeeppowerdown(resume)1:Pin10isusedasEOC/INToutput1:Autonappowerdowndisabled

1:Removedevicefromnappowerdown(resume)

Autonappowerdownenable/disable(midvoltageandcomparatorshutdownbetweencycles).ThisbitsettingisignoredifD9=0.Nappowerdown(midvoltageandcomparatorshutdownbetweencycles).Thisbitissetto1automaticallybywake-upcommand.

1:PinusedasEOC

1:EOCActivelow/INTactivelow

1:Conversionclock(CCLK)=InternalOSC

1:ManualtriggermanuallystartedbyfallingedgeofCONVSTDon'tcare

Trigger(conversionstart)select:startconversionattheendofsampling(EOS).IfD9=0,theD4settingisignored.

1:Autochannelselectenabled.Allchannelsaresampledandconvertedsequentiallyuntilthecycleafterthisbitissetto0.

DEFINITION

D10Default=1D9Default=1D8Default=1D7Default=1D6Default=1D5Default=1D4Default=1D3Default=1D2Default=1D1Default=0:ADS83291:ADS8330D0Default=1

READINGCONVERSIONRESULT

Theconversionresultisavailabletotheinputoftheoutputdataregister(ODR)atEOCandpresentedtotheoutputoftheoutputregisteratthenextfallingedgeofCSorFS.ThehostprocessorcanthenshiftthedataoutviatheSDOpinanytimeexceptduringthequietzone.Thisis20nsbeforeand20nsaftertheendofsampling(EOS)period.Endofsampling(EOS)isdefinedasthefallingedgeofCONVSTwhenmanualtriggerisusedortheendofthe3rdconversionclock(CCLK)afterEOCifautotriggerisused.

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ThefallingedgeofFS/CSshouldnotbeplacedattheprecisemoment(minimumofatleastoneconversionclock(CCLK)delay)attheendofaconversion(bydefaultwhenEOCgoeshigh),otherwisethedataiscorrupt.IfFS/CSisplacedbeforetheendofaconversion,thepreviousconversionresultisread.IfFS/CSisplacedaftertheendofaconversion,thecurrentconversionresultisread.

Theconversionresultis16-bitdatainstraightbinaryformatasshowninTable4.Generally16SCLKsarenecessary,butthereareexceptionswheremorethan16SCLKSarerequired(seeTable5).Dataoutputfromtheserialoutput(SDO)isleftadjustedMSBfirst.ThetrailingbitsarefilledwiththeTAGbitfirst(ifenabled)plusallzeros.SDOremainslowuntilFS/CSisbroughthighagain.

SDOisactivewhenFS/CSislow.TherisingedgeofFS/CS3-statestheSDOoutput.

NOTE:

WheneverSDOisnotin3-state(whenFS/CSislowandSCLKisrunning),aportionoftheconversionresultisoutputattheSDOpin.ThenumberofbitsdependsonhowmanySCLKsaresupplied.Forexample,amanualselectchannelcommandcyclerequires4SCLKs,therefore4MSBsoftheconversionresultareoutputatSDO.TheexceptionisSDOoutputsall1sduringthecycleimmediatelyafteranyreset(PORorsoftwarereset).

IfSCLKisusedastheconversionclock(CCLK)andacontinuousSCLKisused,itisnotpossibletoclockoutall16SDObitsduringthesamplingtime(6SCLKs)becauseofthequietzonerequirement.Inthiscaseitisbettertoreadtheconversionresultduringtheconversiontime(36SCLKsor48SCLKsinautonapmode).

Table5.IdealInputVoltagesandOutputCodes

DESCRIPTION

Fullscalerange

Leastsignificantbit(LSB)FullscaleMidscaleMidscale–1LSBZero

Vref

Vref/65536+Vref–1LSBVref/2Vref/2–1LSB0V

ANALOGVALUE

DIGITALOUTPUTSTRAIGHTBINARYBINARYCODE1111111111111111100000000000000001111111111111110000000000000000

HEXCODEFFFF80007FFF0000

TAGMode

TheADS8330includesafeature,TAG,thatcanbeusedasatagtoindicatewhichchannelsourcedtheconvertedresult.AnaddressbitisaddedaftertheLSBreadoutfromSDOindicatingwhichchanneltheresultcamefromifTAGmodeisenabled.Thisaddressbitis0forchannel0and1forchannel1.Theconverterrequiresmorethanthe16SCLKsthatarerequiredfora4bitcommandplus12bitCFRor16databitsbecauseoftheadditionalTAGbit.ChainMode

TheADS8329/30canoperateasasingleconverterorinasystemwithmultipleconverters.Systemdesignerscantakeadvantageofthesimplehigh-speedSPIcompatibleserialinterfacebycascadingtheminasinglechainwhenmultipleconvertersareused.AbitintheCFRisusedtoreconfiguretheEOC/INTstatuspinasasecondaryserialdatainput,chaindatainput(CDI),fortheconversionresultfromanupstreamconverter.Thisischainmodeoperation.AtypicalconnectionofthreeconvertersisshowninFigure59.

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Micro󰀀ControllerINTGPIO1GPIO2GPIO3SDOSCLKSDISDISCLKCONVSTCSADS8329#1SDOEOC/INTSDISCLKCONVSTCSADS8329#2CDISDOSDISCLKCONVSTCSADS8329#3CDISDOProgram󰀀device󰀀#1󰀀CFR_D[7:5]󰀀=󰀀XX0bProgram󰀀device󰀀#2󰀀and󰀀#3󰀀CFR_D[7:5]󰀀=󰀀XX1b

Figure59.MultipleConvertersConnectedUsingChainMode

Whenmultipleconvertersareusedinchainmode,thefirstconverterisconfiguredinregularmodewhiletherest

oftheconvertersdownstreamareconfiguredinchainmode.Whenaconverterisconfiguredinchainmode,theCDIinputdatagoesstraighttotheoutputregister,thereforetheserialinputdatapassesthroughtheconverterwitha16SCLK(iftheTAGfeatureisdisabled)ora24SCLKdelay,aslongasCSisactive.SeeFigure60fordetailedtiming.Inthistimingtheconversionineachconvertersaredonesimultaneously.

CascadedManual󰀀Trigger/Read󰀀While󰀀Sampling

(Useinternal󰀀CCLK,󰀀EOC󰀀active󰀀low,󰀀andINTactive󰀀low)󰀀󰀀󰀀󰀀󰀀󰀀󰀀heldCSlowduring󰀀the󰀀N󰀀times󰀀16󰀀bits󰀀transfer󰀀cycle.CONVST#1,CONVST#2,CONVST#3EOC󰀀#1(active󰀀low)INT#3

(activelow)CS/FS󰀀#1SCLK󰀀#1,SCLK󰀀#2,SCLK󰀀#3SDO󰀀#1,CDI󰀀#2CS/FS󰀀#2,CS/FS󰀀#3SDO󰀀#2,CDI󰀀#3

Hi-Ztd(SDO-CDI)N−1th󰀀from󰀀#2Nth󰀀from󰀀#1Nth󰀀from󰀀#11.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀161.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀16EOSNthEOCtCONV=󰀀18󰀀CCLKstSAMPLE1=󰀀3󰀀CCLKs󰀀mintd(CSR-EOS)=󰀀20󰀀ns󰀀min1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀16Hi-ZNth󰀀from󰀀#1Hi-Ztd(CSR-EOS)=󰀀20󰀀ns󰀀minHi-ZSDO󰀀#3SDI󰀀#1,SDI󰀀#2,SDI󰀀#3

Hi-Ztd(SDO-CDI)Nth󰀀from󰀀#3N−1th󰀀from󰀀#2Nth󰀀from󰀀#1Hi-Z1110............1101b1101bCONFIGUREREAD󰀀ResultREAD󰀀Result

Figure60.SimplifiedCascadeModeTimingwithSharedCONVSTandContinuousCS32

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CaremustbegiventohandlethemultipleCSsignalswhentheconvertersareoperatinginchainmode.Thedifferentchipselectsignalsmustbelowfortheentiredatatransfer(inthisexample48bitsforthreeconverters).Thefirst16-bitwordafterthefallingchipselectisalwaysthedatafromthechipthatreceivedthechipselectsignal.

Case1:Ifchipselectisnottoggled(CSstayslow),thenext16bitsaredatafromtheupstreamconverter,andsoon.ThisisshowninFigure60.Ifthereisnoupstreamconverterinthechain,asconverter#1intheexample,thesamedatafromtheconverterisgoingtobeshownrepeatedly.

Case2:Ifthechipselectistoggledduringachainmodedatatransfercycle,asillustratedinFigure61,thesamedatafromtheconverterisreadoutagainandagaininallthreediscrete16-bitcycles.Thisisnotadesiredresult.

CascadedManual󰀀Trigger/Read󰀀While󰀀Sampling

(Use󰀀internal󰀀CCLK,󰀀EOC,󰀀andINTpolarity󰀀programmed󰀀as󰀀active󰀀low)CSheld󰀀low󰀀during󰀀the󰀀N󰀀times󰀀16󰀀bits󰀀transfer󰀀cycle.CONVST#1,CONVST#2,CONVST#3EOC󰀀#1(active󰀀low)INT#1

(activelow)CS/FS󰀀#1SCLK󰀀#1,SCLK󰀀#2,SCLK󰀀#3SDO󰀀#1,CDI󰀀#2CS/FS󰀀#2SCLK󰀀󰀀#2,SDO󰀀#2,CDI󰀀#3CS/FS󰀀#3SDO󰀀#3SDI󰀀#1,SDI󰀀#2,SDI󰀀#3

Nth󰀀from󰀀#31110............N−1th󰀀from󰀀#21101b1101bNth󰀀from󰀀#1116116116These󰀀SCLKs󰀀are󰀀optional.EOCEOSNthtCONV=󰀀18󰀀CCLKstSAMPLE1=󰀀3󰀀CCLKs󰀀mintd(EOS-CSF)=󰀀20󰀀ns󰀀mintd(CSR-EOS)=󰀀20󰀀ns󰀀minNthfrom󰀀#1Nth󰀀from󰀀#1Nth󰀀from󰀀#1td(EOS-CSF)=20󰀀ns󰀀mintd(CSR-EOS)=20󰀀ns󰀀minN−1th󰀀from󰀀#2Nth󰀀from󰀀#1td(EOS-CSF)=20󰀀ns󰀀minNth󰀀from󰀀#1td(CSR-EOS)=20󰀀ns󰀀minCONFIGUREREAD󰀀ResultREAD󰀀ResultFigure61.SimplifiedCascadeModeTimingwithSharedCONVSTandDiscreteCSFigure62showsaslightlydifferentscenariowhereCONVSTisnotsharedbythesecondconverter.Converters#1and#3havethesameCONVSTsignal.Inthiscase,converter#2simplypassespreviousconversiondatadownstream.

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CascadedManual󰀀Trigger/Read󰀀While󰀀Sampling

(Use󰀀internal󰀀CCLK,󰀀EOC󰀀active󰀀low󰀀andINTactive󰀀low)CSheld󰀀low󰀀during󰀀the󰀀N󰀀times󰀀16󰀀bits󰀀transfer󰀀cycle.CONVST#1,CONVST#3

Note󰀀:󰀀old󰀀data󰀀shown.EOSEOCEOC󰀀#1(active󰀀low)INT#1

(activelow)CS/FS󰀀#1SCLK󰀀#1,SCLK󰀀#2,SCLK󰀀#3SDO󰀀#1,CDI󰀀#2CS/FS󰀀#2,CS/FS󰀀#3SDO󰀀#2,CDI󰀀#3

NthtCONV=󰀀18󰀀CCLKstSAMPLE1=󰀀3󰀀CCLKs󰀀mintd(CSR-EOS)=󰀀20󰀀ns󰀀min1󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.161.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.161󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.󰀀.16Hi-ZNth󰀀from󰀀#1Hi-Ztd(CSR-EOS)=󰀀20󰀀ns󰀀mintd(SDO-CDI)Hi-ZN−1th󰀀from󰀀#2Nth󰀀from󰀀#1Hi-ZSDO󰀀#3SDI󰀀#1,SDI󰀀#2,SDI󰀀#3

Hi-Ztd(SDO-CDI)Nth󰀀from󰀀#31110............1101bN−1th󰀀from󰀀#2Nth󰀀from󰀀#11101bHi-ZCONFIGUREREAD󰀀ResultREAD󰀀ResultFigure62.SimplifiedCascadeTiming(SeparateCONVST)ThenumberofSCLKsrequiredforaserialreadcycledependsonthecombinationofdifferentreadmodes,TAGbit,chainmode,andthewayachannelisselected,i.e.,autochannelselect.ThisislistedinTable6.

Table6.RequiredSCLKsForDifferentReadOutModeCombinations

CHAINMODEAUTOCHANNEL

TAGENABLEDCFR.D1

ENABLEDCFR.D5SELECTCFR.D11

00001111

00110011

01010101

NUMBEROFSCLKPERSPI

READ

16≥1716≥1716241624

None

MSBisTAGbitpluszero(s)None

TAGbitplus7zerosNone

TAGbitplus7zerosNone

TAGbitplus7zeros

TRAILINGBITS

34

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SCLKskewbetweenconvertersanddatapathdelaythroughtheconvertersconfiguredinchainmodecanaffectthemaximumfrequencyofSCLK.Thedelaycanalsobeaffectedbysupplyvoltageandloading.ItmaybenecessarytoslowdowntheSCLKwhenthedevicesareconfiguredinchainmode.

ADS8329#3CDILogicDelayPlus󰀀PAD2.7󰀀nsDLogicDelay<=8.3nsQLogicDelayPlus󰀀PAD8.3󰀀nsSDOSerial󰀀dataoutputCLKADS8329#2CDILogicDelayPlus󰀀PAD2.7󰀀nsDLogicDelay<=8.3nsQLogicDelayPlus󰀀PAD8.3󰀀nsSDOCLKADS8329#1CDILogicDelayPlus󰀀PAD2.7󰀀nsDLogicDelay<=8.3nsQLogicDelayPlus󰀀PAD8.3󰀀nsSDOSerial󰀀datainputCLKSCLK󰀀input

Figure63.TypicalDelayThroughConvertersConfiguredinChainMode

RESET

Theconverterhastworesetmechanisms,apower-onreset(POR)andasoftwareresetusingCFR_D0.ThesetwomechanismsareNOR-edinternally.Whenareset(softwareorPOR)isissued,allregisterdataaresettothedefaultvalues(all1s)andtheSDOoutput(duringthecycleimmediatelyafterreset)issettoall1s.Thestatemachineisresettothepower-onstate.

SW RESETPORSETSAR ShiftRegisterConversion ClockLatched by End OfConversionEOCEOC

Latched by Falling Edge of CSCS

IntermediateLatchOutputRegisterSDOSCLK

CDIFigure.DigitalOutputUnderResetCondition

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APPLICATIONINFORMATION

TYPICALCONNECTION

Analog +5 V4.7 mFAGNDExt Ref Input22 mFAGND+VAREF+REF−AGNDIN+IN−FS/CSSDOSDISCLKInterfaceSupply +1.8 VBDGND4.7 mFEOC/INT+VBDAnalog InputHostProcessorADS8329CONVSTFigure65.TypicalCircuitConfiguration

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PACKAGINGINFORMATION

OrderableDeviceADS8329IBRSARADS8329IBRSARG4ADS8329IBRSATADS8329IBRSATG4ADS8329IRSARADS8329IRSARG4ADS8329IRSATADS8329IRSATG4ADS8330IBRSARADS8330IBRSARG4ADS8330IBRSATADS8330IBRSATG4ADS8330IRSARADS8330IRSARG4ADS8330IRSATADS8330IRSATG4

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

PackageTypeQFNQFNQFNQFNQFNQFNQFNQFNQFNQFNQFNQFNQFNQFNQFNQFN

PackageDrawingRSARSARSARSARSARSARSARSARSARSARSARSARSARSARSARSA

PinsPackageEcoPlan(2)

Qty16161616161616161616161616161616

3000Green(RoHS&

noSb/Br)3000Green(RoHS&

noSb/Br)250250

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEAR

2000Green(RoHS&

noSb/Br)2000Green(RoHS&

noSb/Br)250250

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

3000Green(RoHS&

noSb/Br)3000Green(RoHS&

noSb/Br)250250

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

3000Green(RoHS&

noSb/Br)3000Green(RoHS&

noSb/Br)250250

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

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(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

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