专利名称：APPARATUS AND METHOD FOR ISSUE
GROUPING OF INSTRUCTIONS IN A VLIWPROCESSOR
发明人：MOHAMED, MOATAZ, A.,LI, CHIEN-WEI,SPENCE, JOHN, R.
申请号：EP01932602申请日：20010423公开号：EP1297417A4公开日：20050824
摘要：An apparatus and method for issue grouping of instructions (204-216) in a VLIWprocessor is disclosed. There can be up to three issue groups in each VLIW packet (200).Template (202) in the VLIW packet (200) comprises two 3-bit, issue group end markers(224, 226) identifying the last instruction of issue group 1 and issue group 2, respectively.Any instructions in the VLIW packet falling outside the first two groups are placed in athird issue group. The template (202) further comprises a chaining bit (228) used to chaininstructions appearing after the last instruction of the last issue group of a first VLIWpacket to the instructions in the first issue group of a second VLIW packet. Maskgeneration logic (612) along with other logic blocks (608, 610, 614, 616) are utilized togenerate a mask to pass through instructions in a VLIW packet (600) which belong to asame issue group for execution in a same clock cycle.
申请人：MINDSPEED TECHNOLOGIES, INC.
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