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93c46

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93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

1K-16K Microwire Compatible Serial EEPROMs

Features:

•Densities from 1 Kbits through 16 Kbits•Low-power CMOS technology

•Available with or without ORG function:With ORG function:

-ORG pin at Logic Low: 8-bit word-ORG pin at Logic High: 16-bit wordWithout ORG function:

-‘A’ version: 8-bit word-‘B’ version: 16-bit wordProgram Enable pin:

-Write-protect for entire array (93XX76C and 93XX86C only)Self-timed Erase/Write cycles (including auto-erase)

Automatic ERAL before WRAL

Power-on/off data protection circuitryIndustry standard 3-wire serial I/ODevice Status signal (Ready/Busy)Sequential Read function1,000,000 E/W cycles

Data retention > 200 yearsPb-free and RoHS compliantTemperature ranges supported:-Industrial (I)-Automotive (E)

-40°C to +85°C-40°C to +125°C

Description:

Microchip Technology Inc. supports the 3-wireMicrowire bus with low-voltage serial ElectricallyErasable PROMs (EEPROM) that range in densityfrom 1 Kbits up to 16 Kbits. Each density is availablewith and without the ORG functionality, and selectedby the part number ordered. Advanced CMOS technol-ogy makes these devices ideal for low-power, nonvol-atile memory applications. The entire series ofMicrowire devices are available in the standard 8-leadPDIP and SOIC packages, as well as the moreadvanced packaging such as the 8-lead MSOP, 8-leadTSSOP, 6-lead SOT-23, and 8-lead DFN (2x3). Allpackages are Pb-free.

•

••••••••••

Pin Diagrams (not to scale)

PDIP/SOIC(P, SN)CS18765VCCPE(2,3)(1,3)ROTATED SOIC(ex: 93LC46BX)(1,3)NCVCCCSCLK12348765ORGVSSDODICLK2DIDO34ORGVSSDFN (MC)CSCLKDIDOTSSOP/MSOP

(ST, MS)12348765VCCPE(2,3)ORG(1,3)VSSSOT-23(OT)VCC(2,3)Pin Function Table

NameCSCLKDIDOVSSPEORGVCCNote:

Chip SelectSerial Data ClockSerial Data InputSerial Data OutputGroundProgram EnableMemory ConfigurationPower Supply

ORG and PE functionality not available inall products. See Table1-1, DeviceSelection Table.

Function

CSCLKDIDO12348765PEVSSORG(1,3)DIVSSDO123654VCCCSCLKNote1:ORG pin: Only on 93XX46C/56C/66C/76C/86C.

2:PE pin: Only on 93XX76C/86C.

3:ORG/PE: No internal connections on 93XXA/B.

93XX46X/56X/66X/76X/86X

TABLE 1-1:

Part Number93XX46A/B/C93AA46A93AA46B93AA46C93LC46A93LC46B93LC46C93C46A93C46B93C46C93AA46AX93AA46BX93AA46CX93LC46AX93LC46BX93LC46CX93C46AX93C46BX93C46CX93XX56A/B/C93AA56A93AA56B93AA56C93LC56A93LC56B93LC56C93C56A93C56B93C56C93XX66A/B/C93AA66A93AA66B93AA66C93LC66A93LC66B93LC66C93C66A93C66B93C66C

444444444

1.8-5.51.8-5.51.8-5.52.5-5.52.5-5.52.5-5.54.5-5.54.5-5.54.5-5.5

NoNoYesNoNoYesNoNoYes

512 x 8 bits256 x 16 bitsSelectable x8 or x16

NoNoNoNoNoNoNoNoNo

IIII, EI, EI, EI, EI, EI, E

P, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MC

222222222

1.8-5.51.8-5.51.8-5.52.5-5.52.5-5.52.5-5.54.5-5.54.5-5.54.5-5.5

NoNoYesNoNoYesNoNoYes

256 x 8 bits128 x 16 bitsSelectable x8 or x16

NoNoNoNoNoNoNoNoNo

IIII, EI, EI, EI, EI, EI, E

P, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MC

111111111111111111

1.8-5.51.8-5.51.8-5.52.5-5.52.5-5.52.5-5.54.5-5.54.5-5.54.5-5.51.8-5.51.8-5.51.8-5.52.5-5.52.5-5.52.5-5.54.5-5.54.5-5.54.5-5.5

NoNoYesNoNoYesNoNoYesNoNoYesNoNoYesNoNoYes

128 x 8 bits64 x 16 bitsSelectable x8 or x16

NoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo

IIII, EI, EI, EI, EI, EI, EIIII, EI, EI, EI, EI, EI, E

P, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, OT, MCP, SN, ST, MS, MC

DEVICE SELECTION TABLE

Density(Kbits)

VCC Range

ORG Pin

Organization (Words)

PE Pin

Temp Range

Packages

93AA46AX/BX/CX, 93LC46AX/BX/CX, 93C46AX/BX/CX (Alternate pinout with die rotated 90°)

93XX46X/56X/66X/76X/86X

TABLE 1-1:

Part Number93XX76A/B/C93AA76A93AA76B93AA76C93LC76A93LC76B93LC76C93C76A93C76B93C76C93XX86A/B/C93AA86A93AA86B93AA86C93LC86A93LC86B93LC86C93C86A93C86B93C86C

161616161616161616

1.8-5.51.8-5.51.8-5.52.5-5.52.5-5.52.5-5.54.5-5.54.5-5.54.5-5.5

NoNoYesNoNoYesNoNoYes

2048 x 8 bits1024 x 16 bitsSelectable x8 or x16

NoNoYesNoNoYesNoNoYes

IIII, EI, EI, EI, EI, EI, E

OTOT

P, SN, ST, MS, MCOTOT

P, SN, ST, MS, MC

888888888

1.8-5.51.8-5.51.8-5.52.5-5.52.5-5.52.5-5.54.5-5.54.5-5.54.5-5.5

NoNoYesNoNoYesNoNoYes

1024 x 8 bits512 x 16 bitsSelectable x8 or x16

NoNoYesNoNoYesNoNoYes

IIII, EI, EI, EI, EI, EI, E

OTOT

P, SN, ST, MS, MCOTOT

P, SN, ST, MS, MC

DEVICE SELECTION TABLE (CONTINUED)

Density(Kbits)

VCC Range

ORG Pin

Organization (Words)

PE Pin

Temp Range

Packages

93XX46X/56X/66X/76X/86X

2.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0VAll inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0VStorage temperature...............................................................................................................................-65°C to +150°CAmbient temperature with power applied................................................................................................-40°C to +125°CESD protection on all pins......................................................................................................................................................≥4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions forextended periods may affect device reliability.

TABLE 2-1:DC CHARACTERISTICS

VCC = 1.8V to 5.5VIndustrial (I): TA = -40°C to +85°CAutomotive (E): TA = -40°C to +125°CMin.2.00.7 VCC-0.3-0.3——2.4VCC-0.2——————

Typ.—————————————500——100——

Max.VCC +1VCC +10.80.2 VCC0.40.2——±1±1723—1500—15

UnitsVVVVVVVVμAμApFmAmAμAmAμAμAμAμA

Conditions

VCC ≥ 2.7VVCC < 2.7VVCC ≥ 2.7VVCC < 2.7V

IOL = 2.1 mA, VCC = 4.5VIOL = 100 μA, VCC = 2.5VIOH = -400 μA, VCC = 4.5VIOH = -100 μA, VCC = 2.5VVIN = VSS to VCCVOUT = VSS to VCCVIN/VOUT = 0V (Note 1)TA = 25°C, FCLK = 1 MHzFCLK = 3 MHz, VCC = 5.5V (93XX46X/56X/66X)FCLK = 3 MHz, VCC = 5.5V (93XX76X/86X)

FCLK = 2 MHz, VCC = 2.5VFCLK = 3 MHz, VCC = 5.5VFCLK = 2 MHz, VCC = 3.0VFCLK = 2 MHz, VCC = 2.5VI-Temp (Note 2, 3)E-Temp

CLK = Cs = 0V

ORG = DI = VSS or VCC93AAX6A/B/C, 93LCX6A/B/C, 93CX6A/B/C (Note 1)

All parameters apply over the specified ranges unless otherwise noted.Param.

Symbol

No.D1D2D3D4D5D6D7D8

VIH1VIH2VIL1VIL2VOL1VOL2VOH1VOH2ILIILOCIN, COUT

Parameter

High-level input voltageLow-level input voltageLow-level output voltageHigh-level output voltageInput leakage currentOutput leakage currentPin capacitance (all inputs/outputs)

ICC writeWrite current

D9ICC readRead current

—————

D10ICCSStandby current

D11Note1:

2:3:

VPORVCC voltage detect

——1.5V3.8V——VV

This parameter is periodically sampled and not 100% tested.ORG and PE pins not available on ‘A’ or ‘B’ versions.

Ready/Busy status must be cleared from DO, see Section4.4 “Data Out (DO)”.

93XX46X/56X/66X/76X/86X

TABLE 2-2:

AC CHARACTERISTICS

VCC = 1.8V to 5.5VIndustrial (I): TA = -40°C to +85°CAutomotive (E): TA = -40°C to +125°CMin.—

Max.321—

UnitsMHzMHzMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsms

Conditions

4.5V ≤ VCC < 5.5V2.5V ≤ VCC < 4.5V1.8V ≤ VCC < 2.5V4.5V ≤ VCC < 5.5V2.5V ≤ VCC < 4.5V1.8V ≤ VCC < 2.5V4.5V ≤ VCC < 5.5V2.5V ≤ VCC < 4.5V1.8V ≤ VCC < 2.5V4.5V ≤ VCC < 5.5V2.5V ≤ VCC < 4.5V1.8V ≤ VCC < 2.5V1.8V ≤ VCC < 5.5V1.8V ≤ VCC < 5.5V4.5V ≤ VCC < 5.5V2.5V ≤ VCC < 4.5V1.8V ≤ VCC < 2.5V4.5V ≤ VCC < 5.5V2.5V ≤ VCC < 4.5V1.8V ≤ VCC < 2.5V

4.5V ≤ VCC < 5.5V, CL = 100 pF (93C76X/86X)

4.5V ≤ VCC < 5.5V, CL = 100 pF2.5V ≤ VCC < 4.5V, CL = 100 pF1.8V ≤ VCC < 2.5V, CL = 100 pF4.5V ≤ VCC < 5.5V, (Note 1)1.8V ≤ VCC < 4.5V, (Note 1)4.5V ≤ VCC < 5.5V, CL = 100 pF2.5V ≤ VCC < 4.5V, CL = 100 pF1.8V ≤ VCC < 2.5V, CL = 100 pFErase/Write mode93XX76X/86X

(AA and LC versions)93XX46X/56X/66X (AA and LC versions) 93C46X/56X/66X/76X/86XERAL mode, 4.5V ≤ VCC ≤ 5.5V WRAL mode, 4.5V ≤ VCC ≤ 5.5V

All parameters apply over the specified ranges unless otherwise noted.Param.

Symbol

No.A1

FCLK

Parameter

Clock frequency

A2TCKHClock high time

2002504501002004505010025002505010025050100250——

A3TCKLClock low time—

A4TCSSChip Select setup time—

A5A6A7

TCSHTCSLTDIS

Chip Select hold timeChip Select low timeData input setup time

———

A8TDIHData input hold time—

A9TPDData output delay time1002002504001002002003005005

A10A11

TCZTSV

Data output disable timeStatus valid time

——

A12TWCProgram cycle time—

—

A13A14A15A16Note1:

TWCTECTWL—

EnduranceProgram cycle time

———1M

62615—

msmsmsms

cycles25°C, VCC = 5.0V, (Note 2)

This parameter is periodically sampled and not 100% tested.

This application is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which may be downloaded from Microchip’s web site at www.microchip.com.

93XX46X/56X/66X/76X/86X

FIGURE 2-1:

VIHVIL

CLK

VIHVIL

TDIS

VIHVIL

DO(Read)

VOHVOL

TSV

Status Valid

TPD

TDIH

TCSS

TCKH

TCKL

TCSH

SYNCHRONOUS DATA TIMING

TCZ

DOVOH

(Program)

VOLNote:

Status Valid Time (TSV) is relative to CS.

93XX46X/56X/66X/76X/86X

TABLE 2-3:

InstructionSB

INSTRUCTION SET FOR 93XX46A/B/C

Opcode

Address

Data In

Data Out

Req. CLK Cycles

93XX46B OR 93XX46C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

A5A4A3A2A1A0101

001

xxx

—————

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD15-D0

9999252525

A5A4A3A2A1A0

A5A4A3A2A1A0D15-D0(RDY/BSY)0

D15-D0(RDY/BSY)

93XX46A OR 93XX46C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

A6A5A4A3A2A1A0101

001

xxx

—————D7-D0D7-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD7-D0(RDY/BSY)(RDY/BSY)10101010181818

A6A5A4A3A2A1A0A6A5A4A3A2A1A00

TABLE 2-4:

InstructionSB

INSTRUCTION SET FOR 93XX56A/B/C

Opcode

Address

Data In

Data Out

Req. CLK Cycles

93XX56B OR 93XX56C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

x101xx0

A6A5A4A3A2A1A0001

xxx

—————

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD15-D0(RDY/BSY)(RDY/BSY)

11111111272727

A6A5A4A3S2A1A0

A6A5A4A3S2A1A0D15-D01

D15-D0

93XX56A OR 93XX56C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

x101xx0

A7A6A5A4A3A2A1A0001

xxx

—————D7-D0D7-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD7-D0(RDY/BSY)(RDY/BSY)

12121212202020

A7A6A5A4A3A2A1A0A7A6A5A4A3A2A1A01

93XX46X/56X/66X/76X/86X

TABLE 2-5:

InstructionSB

INSTRUCTION SET FOR 93XX66A/B/C

Opcode

Address

Data In

Data Out

Req. CLK Cycles

93XX66B OR 93XX66C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

A7A6A5A4A3A2A1A0101

001

xxx

—————D15-D0D15-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD15-D0(RDY/BSY)(RDY/BSY)11111111272727

A7A6A5A4A3A2A1A0A7A6A5A4A3A2A1A00

93XX66A OR 93XX66C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

A8A7A6A5A4A3A2A1A0101

001

xxx

—————D7-D0D7-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD7-D0(RDY/BSY)(RDY/BSY)

12121212202020

A8A7A6A5A4A3A2A1A0A8A7A6A5A4A3A2A1A00

TABLE 2-6:

InstructionSB

INSTRUCTION SET FOR 93XX76A/B/C

Opcode

Address

Data In

Data Out

Req. CLK Cycles

93XX76B OR 93XX76C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

x101xx0

A8A7A6A5A4A3A2A1A0001

xxx

—————D15-D0D15-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD15-D0(RDY/BSY)(RDY/BSY)

13131313292929

A8A7A6A5A4A3A2A1A0A8A7A6A5A4A3A2A1A01

93XX76A OR 93XX76C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

x101xx0

A9A8A7A6A5A4A3A2A1A0001

xxx

—————D7-D0D7-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD7-D0(RDY/BSY)(RDY/BSY)

14141414222222

A9A8A7A6A5A4A3A2A1A0A9A8A7A6A5A4A3A2A1A01

93XX46X/56X/66X/76X/86X

TABLE 2-7:

Instruction

INSTRUCTION SET FOR 93XX86A/B/C

Opcode

Address

Data In

Data Out

Req. CLK Cycles

93XX86B OR 93XX86C WITH ORG = 1 (16-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

A9A8A7A6A5A4A3A2A1A0101

001

xxx

—————D15-D0D15-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD15-D0(RDY/BSY)(RDY/BSY)13131313292929

A9A8A7A6A5A4A3A2A1A0A9A8A7A6A5A4A3A2A1A00

93XX86A OR 93XX86C WITH ORG = 0 (8-BIT WORD ORGANIZATION)

ERASEERALEWDSEWENREADWRITEWRAL

1111111

11000000100100

A10A9A8A7A6A5A4A3A2A1A0101

001

xxx

—————D7-D0D7-D0

(RDY/BSY)(RDY/BSY)High-ZHigh-ZD7-D0(RDY/BSY)(RDY/BSY)

14141414222222

A10A9A8A7A6A5A4A3A2A1A0A10A9A8A7A6A5A4A3A2A1A00

93XX46X/56X/66X/76X/86X

3.0

FUNCTIONAL DESCRIPTION

3.3

Data Protection

When the ORG pin is connected to VCC, the (x16)organization is selected. When it is connected toground, the (x8) organization is selected. Instruc-tions, addresses and write data are clocked into theDI pin on the rising edge of the clock (CLK). The DOpin is normally held in a High-Z state except whenreading data from the device, or when checking theReady/Busy status during a programming operation.The Ready/Busy status can be verified during anErase/Write operation by polling the DO pin; DO lowindicates that programming is still in progress, whileDO high indicates the device is ready. DO will enterthe High-Z state on the falling edge of CS.

All modes of operation are inhibited when VCC is belowa typical voltage of 1.5V for ‘93AAXX’ and ‘93LCXX’devices or 3.8V for ‘93CXX’ devices.

The EWEN and EWDS commands give additionalprotection against accidentally programming duringnormal operation.Note:

For added protection, an EWDS commandshould be performed after every writeoperation and an external 10 kΩ pull-downprotection resistor should be added to theCS pin.

3.1Start Condition

The Start bit is detected by the device if CS and DI areboth high with respect to the positive edge of CLK forthe first time.

Before a Start condition is detected, CS, CLK and DImay change in any combination (except to that of aStart condition), without resulting in any deviceoperation (Read, Write, Erase, EWEN, EWDS, ERALor WRAL). As soon as CS is high, the device is nolonger in Standby mode.

An instruction following a Start condition will only beexecuted if the required opcode, address and data bitsfor any particular instruction are clocked in.Note:

When preparing to transmit an instruction,either the CLK or DI signal levels must beat a logic low as CS is toggled active high.

After power-up, the device is automatically in theEWDS mode. Therefore, an EWEN instruction must beperformed before the initial ERASE or WRITE instructioncan be executed.Note:

To prevent accidental writes to the array inthe 93XX76C/86C devices, set the PE pinto a logic low.

Block Diagram

VCCVSS

HV Generator

I/O ControlLogic

MemoryControlLogic

XDec

EEPROMArrayByte Latches

3.2Data In/Data Out (DI/DO)

Y Decoder

DIDOCSCLKORG(1)PE(2)

It is possible to connect the Data In and Data Out pinstogether. However, with this configuration it is possiblefor a “bus conflict” to occur during the “dummy zero”that precedes the read operation, if A0 is a logic highlevel. Under such a condition the voltage level seen atData Out is undefined and will depend upon the relativeimpedances of Data Out and the signal source drivingA0. The higher the current sourcing capability of thedriver, the higher the voltage at the Data Out pin. Inorder to limit this current, a resistor should beconnected between DI and DO.

Sense Amp.R/W Control

Note1:ORG pin: Only on 93XX46C/56C/66C/76C/86C.

2:PE pin: Only on 93XX76C/86C.

93XX46X/56X/66X/76X/86X

3.4

ERASE

The ERASE instruction forces all data bits of thespecified address to the logical ‘1’ state. CS is broughtlow following the loading of the last address bit. Thisfalling edge of the CS pin initiates the self-timedprogramming cycle, except on ‘93CXX’ devices wherethe rising edge of CLK before the last address bitinitiates the write cycle.

The DO pin indicates the Ready/Busy status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL). DO at logical ‘0’ indicates that programmingis still in progress. DO at logical ‘1’ indicates that theregister at the specified address has been erased andthe device is ready for another instruction.Note:

After the Erase cycle is complete, issuinga Start bit and then taking CS low will clearthe Ready/Busy status from DO.

FIGURE 3-1:ERASE TIMING FOR 93AAXX AND 93LCXX DEVICES

TCSL

Check Status

CLK

High-Z

111ANAN-1AN-2•••A0

TSV

BUSYTWC

Ready

TCZHigh-Z

FIGURE 3-2:ERASE TIMING FOR 93CXX DEVICES

TCSL

Check Status

CLK

High-Z

111ANAN-1AN-2•••A0

TSV

BusyTWC

Ready

TCZHigh-Z

93XX46X/56X/66X/76X/86X

3.5

ERASE ALL (ERAL)

The Erase All (ERAL) instruction will erase the entirememory array to the logical ‘1’ state. The ERAL cycleis identical to the Erase cycle, except for the differentopcode. The ERAL cycle is completely self-timed andcommences at the falling edge of the CS, except on‘93CXX’ devices where the rising edge of CLK beforethe last data bit initiates the write cycle. Clocking of theCLK pin is not necessary after the device has enteredthe ERAL cycle.

The DO pin indicates the Ready/Busy status of thedevice, if CS is brought high after a minimum of 250 nslow (TCSL).

VCC must be ≥ 4.5V for proper operation of ERAL.Note:

After the ERAL command is complete,issuing a Start bit and then taking CS lowwill clear the Ready/Busy status from DO.

FIGURE 3-3:ERAL TIMING FOR 93AAXX AND 93LCXX DEVICES

TCSL

Check Status

CLK

DIDO

High-Z

10010

X•••X

TSVBusyTEC

Vcc must be ≥ 4.5V for proper operation of ERAL.

Ready

TCZHigh-Z

FIGURE 3-4:ERAL TIMING FOR 93CXX DEVICES

TCSLCSCheck Status

CLK

High-Z

10010

X•••X

TSV

BusyTEC

ReadyTCZHigh-Z

93XX46X/56X/66X/76X/86X

3.6

ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)

The 93XX series devices power-up in the Erase/WriteDisable (EWDS) state. All programming modes mustbe preceded by an Erase/Write Enable (EWEN) instruc-tion. Once the EWEN instruction is executed, program-ming remains enabled until an EWDS instruction isexecuted or VCC is removed from the device. To protect against accidental data disturbance, theEWDS instruction can be used to disable all Erase/Writefunctions and should follow all programmingoperations. Execution of a READ instruction isindependent of both the EWEN and EWDS instructions.

FIGURE 3-5:EWDS TIMING

TCSL

CLK

10000x•••x

FIGURE 3-6:EWEN TIMING

TCSL

CSCLK

10011x

•••

93XX46X/56X/66X/76X/86X

3.7

READ

The READ instruction outputs the serial data of theaddressed memory location on the DO pin. A dummyzero bit precedes the 8-bit (If ORG pin is low or A-versiondevices) or 16-bit (If ORG pin is high or B-versiondevices) output string. The output data bits will toggle onthe rising edge of the CLK and are stable after the spec-ified time delay (TPD). Sequential read is possible whenCS is held high. The memory data will automatically cycleto the next register and output sequentially.

FIGURE 3-7:

READ TIMING

CLKDI

•••A0

High-Z

0Dx•••D0Dx•••D0Dx•••D0

93XX46X/56X/66X/76X/86X

3.8

WRITE

The WRITE instruction is followed by 8 bits (If ORG islow or A-version devices) or 16 bits (If ORG pin is highor B-version devices) of data which are written into thespecified address. For 93AAXX and 93LCXX devices,after the last data bit is clocked into DI, the falling edgeof CS initiates the self-timed auto-erase and program-ming cycle. For 93CXX devices, the self-timed auto-erase and programming cycle is initiated by the risingedge of CLK on the last data bit.

The DO pin indicates the Ready/Busy status of thedevice, if CS is brought high after a minimum of 250 nslow (TCSL). DO at logical ‘0’ indicates that programmingis still in progress. DO at logical ‘1’ indicates that theregister at the specified address has been written withthe data specified and the device is ready for anotherinstruction.Note:

For devices with PE functionality such asthe 93XX76C or 93XX86C, the writesequence requires a logic high signal onthe PE pin prior to the rising edge of clockon the last data bit.

Note:

After the Write cycle is complete, issuing aStart bit and then taking CS low will clearthe Ready/Busy status from DO.

FIGURE 3-8:WRITE TIMING FOR 93AAXX AND 93LCXX DEVICES

TCSL

CLK

101An•••A0Dx•••D0

TSV

High-Z

BusyTwcReady

TCZHigh-ZFIGURE 3-9:

WRITE TIMING FOR 93CXX DEVICES

TCSL

CLK

101An•••A0Dx•••D0

TSV

High-Z

TwcBusy

Ready

93XX46X/56X/66X/76X/86X

3.9

WRITE ALL (WRAL)

The Write All (WRAL) instruction will write the entirememory array with the data specified in the command.For 93AAXX and 93LCXX devices, after the last databit is clocked into DI, the falling edge of CS initiates theself-timed auto-erase and programming cycle. For93CXX devices, the self-timed auto-erase and pro-gramming cycle is initiated by the rising edge of CLK onthe last data bit. Clocking of the CLK pin is not neces-sary after the device has entered the WRAL cycle. TheWRAL command does include an automatic ERALcycle for the device. Therefore, the WRAL instructiondoes not require an ERAL instruction, but the chip mustbe in the EWEN status.

The DO pin indicates the Ready/Busy status of thedevice if CS is brought high after a minimum of 250 nslow (TCSL).

VCC must be ≥ 4.5V for proper operation of WRAL.Note:

For devices with PE functionality such asthe 93XX76C or 93XX86C, the writesequence requires a logic high signal onthe PE pin prior to the rising edge of clockon the last data bit.

After the Write All cycle is complete,issuing a Start bit and then taking CS lowwill clear the Ready/Busy status from DO.

Note:

FIGURE 3-10:WRAL TIMING FOR 93AAXX AND 93LCXX DEVICES

TCSL

CLK

•••Dx

•••DI

xD0

TSV

High-Z

BusyTWL

VCC must be ≥ 4.5V for proper operation of WRAL.

Ready

TCZ

HIGH-Z

FIGURE 3-11:WRAL TIMING FOR 93CXX DEVICES

TCSL

CLK

10001

X•••xDx•••D0

TSV

High-Z

BusyReadyTCZ

HIGH-Z

TWL

93XX46X/56X/66X/76X/86X

4.0

PIN DESCRIPTIONS

SOIC/PDIP/MSOP/TSSOP/DFN

12345678

SOT-2354312N/AN/A6

Chip SelectSerial ClockData InData OutGround

Organization (93XX46C/56C/66C/76C/86C)No connect on 93XXA/B devicesProgram Enable (93XX76C/86C)No connect on 93XXA/B devicesPower Supply

Function

TABLE 4-1:

NameCSCLKDIDOVSSORGNC(1)PENC(1)VCC

Note1:With no internal connection, logic levels on NC pins are “don’t cares.”

4.1Chip Select (CS)

A high level selects the device; a low level deselectsthe device and forces it into Standby mode. However, aprogramming cycle which is already in progress will becompleted, regardless of the Chip Select (CS) inputsignal. If CS is brought low during a program cycle, thedevice will go into Standby mode as soon as theprogramming cycle is completed.

CS must be low for 250 ns minimum (TCSL) betweenconsecutive instructions. If CS is low, the internalcontrol logic is held in a Reset status.

After detection of a Start condition the specified numberof clock cycles (respectively low-to-high transitions ofCLK) must be provided. These clock cycles arerequired to clock in all required opcode, address anddata bits before an instruction is executed. CLK and DIthen become “don't care” inputs waiting for a new Startcondition to be detected.

4.3Data In (DI)

Data In (DI) is used to clock in a Start bit, opcode,address and data synchronously with the CLK input.

4.2Serial Clock (CLK)

4.4Data Out (DO)

The Serial Clock is used to synchronize the communi-cation between a master device and the 93XX seriesdevice. Opcodes, address and data bits are clocked inon the positive edge of CLK. Data bits are also clockedout on the positive edge of CLK.

CLK can be stopped anywhere in the transmissionsequence (at high or low level) and can be continuedanytime with respect to Clock High Time (TCKH) andClock Low Time (TCKL). This gives the controlling mas-ter freedom in preparing opcode, address and data.CLK is a “don't care” if CS is low (device deselected). IfCS is high, but the Start condition has not beendetected (DI = 0), any number of clock cycles can bereceived by the device without changing its status (i.e.,waiting for a Start condition).

CLK cycles are not required during the self-timed Write(i.e., auto Erase/Write) cycle.

Data Out (DO) is used in the Read mode to output datasynchronously with the CLK input (TPD after thepositive edge of CLK).

This pin also provides Ready/Busy status informationduring Erase and Write cycles. Ready/Busy statusinformation is available on the DO pin if CS is broughthigh after being low for minimum Chip Select Low Time(TCSL) and an erase or write operation has beeninitiated.

The Status signal is not available on DO, if CS is heldlow during the entire Erase or Write cycle. In this case,DO is in the High-Z mode. If status is checked after theErase/Write cycle, the data line will be high to indicatethe device is ready.Note:

93XX46X/56X/66X/76X/86X

4.5

Organization (ORG)

4.6

Program Enable (PE)

When the ORG pin is connected to VCC or Logic HI, the(x16) memory organization is selected. When the ORGpin is tied to VSS or Logic LO, the (x8) memoryorganization is selected. For proper operation, ORGmust be tied to a valid logic level.

For devices without the ORG functionality, there is nointernal connection to the ORG pin. In these devicesthe functionality has been set at the factory to supporta single word size.

‘A’ series devices – x8 organization‘B’ series devices – x16 organization

A logic level on the PE pin will enable or disable the abil-ity to write data to the memory array in only the 8-lead93XX76C and 93XX86C devices. For all other devicesthe PE function is not present and the PE pin is a noconnect. When driving the PE pin to a logic High, thedevice can be programmed, but when the PE pin isdriven Low, programming is inhibited. This pin is usedin parallel with the EWEN/EWDS latch to protect thememory array from inadvertent writes, as shown inTable4-2.

In either the 93XX76C or 93XX86C devices, the PE pinmust be tied to a specific logic level and cannot befloated. In all other devices without the PE function, thePE pin has no internal connections and programming isalways enabled.

TABLE 4-2:WRITE PROTECTION SCHEME

PE Pin*1100

Array WRITE

YesNoNoNo

EnabledDisabledEnabledDisabled

EWEN/EWDS Latch

* PE pin level does not alter the state of the EWEN/EWDS latch.Note:

For devices with PE functionality such as 93XX76C or 93XX86C, the write sequence requires a logic highsignal on the PE pin prior to the rising edge of clock on the last data bit.

93XX46X/56X/66X/76X/86X

APPENDIX A:

Revision A

Original release of document. Combined all the 93-SeriesMicrowire Serial EEPROM device data sheets.

REVISION HISTORY

Revision B

Revised 2x3 (MC) DFN package drawing.

Revision C

Correction to Table 2-6, 93XX76A (EWDS).

Revision D (03/2007)

Revised Description; Delete Pb-free notes; ReplacedPackage Drawings; Revised Product ID System.

93XX46X/56X/66X/76X/86X

5.0

5.1

PACKAGING INFORMATION

Package Marking Information

8-Lead PDIP

XXXXXXXXTXXXXNNNYYWWExample: Pb-free

93LC46AI/P IL7e305283-Wire 8-Lead PDIP Package Marking

Part93AA46A93AA46B93AA46C93AA56A93AA56B93AA56C93AA66A93AA66B93AA66C93AA76A93AA76B93AA76C93AA86A93AA86B93AA86CNote:

Line 1 Marking93AA46A93AA46B93AA46C93AA56A93AA56B93AA56C93AA66A93AA66B93AA66C93AA76A93AA76B93AA76C93AA86A93AA86B93AA86C

Part93LC46A93LC46B93LC46C93LC56A93LC56B93LC56C93LC66A93LC66B93LC66C93LC76A93LC76B93LC76C93LC86A93LC86B93LC86C

Line 1 Marking93LC46A93LC46B93LC46C93LC56A93LC56B93LC56C93LC66A93LC66B93LC66C93LC76A93LC76B93LC76C93LC86A93LC86B93LC86C

Part93C46A93C46B93C46C93C56A93C56B93C56C93C66A93C66B93C66C93C76A93C76B93C76C93C86A93C86B93C86C

Line 1 Marking

93C46A93C46B93C46C93C56A93C56B93C56C93C66A93C66B93C66C93C76A93C76B93C76C93C86A93C86B93C86C

Temperature range on second line.Legend:XX...XTYYYWWNNN e3Note:Part number or part number codeTemperature (I, E)Year code (last digit of calendar year)Year code (last 2 digits of calendar year)Week code (week of January 1 is week ‘01’)Alphanumeric traceability code (2 characters for small packages)Pb-free JEDEC designator for Matte Tin (Sn)For very small packages with no room for the Pb-free JEDEC designator , the marking will only appear on the outer carton or reel label.e3In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.Note:DS21929D-page 20© 2007 Microchip Technology Inc.

93XX46X/56X/66X/76X/86X

8-Lead SOIC

Example: Pb-free

XXXXXXXTXXXXYYWWNNN93LC46AISN 0528e31L73-Wire 8-Lead SOIC (SN) Package Marking

Part93AA46A93AA46B93AA46C93AA56A93AA56B93AA56C93AA66A93AA66B93AA66C93AA76A93AA76B93AA76C93AA86A93AA86B93AA86CNote:

Line 1 Marking93AA46AT93AA46BT93AA46CT93AA56AT93AA56BT93AA56CT93AA66AT93AA66BT93AA66CT93AA76AT93AA76BT93AA76CT93AA86AT93AA86BT93AA86CT

Part93LC46A93LC46B93LC46C93LC56A93LC56B93LC56C93LC66A93LC66B93LC66C93LC76A93LC76B93LC76C93LC86A93LC86B93LC86C

Line 1 Marking93LC46AT93LC46BT93LC46CT93LC56AT93LC56BT93LC56CT93LC66AT93LC66BT93LC66CT93LC76AT93LC76BT93LC76CT93LC86AT93LC86BT93LC86CT

Part93C46A93C46B93C46C93C56A93C56B93C56C93C66A93C66B93C66C93C76A93C76B93C76C93C86A93C86B93C86C

Line 1 Marking93C46AT93C46BT93C46CT93C56AT93C56BT93C56CT93C66AT93C66BT93C66CT93C76AT93C76BT93C76CT93C86AT93C86BT93C86CT

T = Temperature Range: I = Industrial, E = Extended

Legend:XX...XTYYYWWNNN e3Note:Part number or part number codeTemperature (I, E)Year code (last digit of calendar year)Year code (last 2 digits of calendar year)Week code (week of January 1 is week ‘01’)Alphanumeric traceability code (2 characters for small packages)Pb-free JEDEC designator for Matte Tin (Sn)For very small packages with no room for the Pb-free JEDEC designator , the marking will only appear on the outer carton or reel label.e3In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.Note:© 2007 Microchip Technology Inc.DS21929D-page 21

93XX46X/56X/66X/76X/86X

Example:

304506L78-Lead 2x3 DFN

XXXYWWNN3-Wire 2x3 DFN Package Marking

Part93AA46A93AA46B93AA46C93AA56A93AA56B93AA56C93AA66A93AA66B93AA66C93AA76C93AA86C

Industrial Line 1 Marking3013113213313413513613713813B13E1

E-Temp Line 1 Marking3023123223323423523623723823B23E2

Part93LC46A93LC46B93LC46C93LC56A93LC56B93LC56C93LC66A93LC66B93LC66C93LC76C93LC86C

Industrial Line 1 Marking3043143243343443543643743843B43E4

E-Temp Line 1 Marking3053153253353453553653753853B53E5

Part93C46A93C46B93C46C93C56A93C56B93C56C93C66A93C66B93C66C93C76C93C86C

Industrial Line 1 Marking3073173273373473573673773873B73E7

E-Temp Line 1 Marking3083183283383483583683783883B83E8

93XX46X/56X/66X/76X/86X

6-Lead SOT-23

XXNN

Example:

1EL7

3-Wire 6-Lead SOT-23 Package Marking

Part93AA46A93AA46B93AA56A93AA56B93AA66A93AA66B93AA76A93AA76B93AA86A93AA86B

Industrial Line 1 Marking1BNN1LNN2BNN2LNN3BNN3LNN4BNN4LNN5BNN5LNN

E-Temp Line 1 Marking1CNN1MNN2CNN2MNN3CNN3MNN4CNN4MNN5CNN5MNN

Part93LC46A93LC46B93LC56A93LC56B93LC66A93LC66B93LC76A93LC76B93LC86A93LC86B

Industrial Line 1 Marking1ENN1PNN2ENN2PNN3ENN3PNN4ENN4PNN5ENN5PNN

E-Temp Line 1 Marking1FNN1RNN2FNN2RNN3FNN3RNN4FNN4RNN5FNN5RNN

Part93C46A93C46B93C56A93C56B93C66A93C66B93C76A93C76B93C86A93C86B

Industrial Line 1 Marking1HNN1TNN2HNN2TNN3HNN3TNN4HNN4TNN5HNN5TNN

E-Temp Line 1 Marking1JNN1UNN2JNN2UNN3JNN3UNN4JNN4UNN5JNN5UNN

93XX46X/56X/66X/76X/86X

8-Lead MSOP (150 mil)

Example:

3L46AI 5281L7XXXXXXTYWWNNN3-Wire 8-Lead MSOP Package Marking

Part93AA46A93AA46B93AA46C93AA56A93AA56B93AA56C93AA66A93AA66B93AA66C93AA76A93AA76B93AA76C93AA86A93AA86B93AA86CNote:

Line 1 Marking

3A46AT3A46BT3A46CT3A56AT3A56BT3A56CT3A66AT3A66BT3A66CT3A76AT3A76BT3A76CT3A86AT3A86BT3A86CT

Part93LC46A93LC46B93LC46C93LC56A93LC56B93LC56C93LC66A93LC66B93LC66C93LC76A93LC76B93LC76C93LC86A93LC86B93LC86C

Line 1 Marking

3L46AT3L46BT3L46CT3L56AT3L56BT3L56CT3L66AT3L66BT3L66CT3L76AT3L76BT3L76CT3L86AT3L86BT3L86CT

Part93C46A93C46B93C46C93C56A93C56B93C56C93C66A93C66B93C66C93C76A93C76B93C76C93C86A93C86B93C86C

Line 1 Marking

3C46AT3C46BT3C46CT3C56AT3C56BT3C56CT3C66AT3C66BT3C66CT3C76AT3C76BT3C76CT3C86AT3C86BT3C86CT

T = Temperature Range: I = Industrial, E = Extended

93XX46X/56X/66X/76X/86X

8-Lead TSSOP

XXXXTYWWNNNExample: L46AI5281L73-Wire 8-Lead TSSOP Package Marking

Part93AA46A93AA46B93AA46C93AA56A93AA56B93AA56C93AA66A93AA66B93AA66C93AA76A93AA76B93AA76C93AA86A93AA86B93AA86CNote:

Line 1 Marking

A46AA46BA46CA56AA56BA56CA66AA66BA66CA76AA76BA76CA86AA86BA86C

Part93LC46A93LC46B93LC46C93LC56A93LC56B93LC56C93LC66A93LC66B93LC66C93LC76A93LC76B93LC76C93LC86A93LC86B93LC86C

Line 1 Marking

L46AL46BL46CL56AL56BL56CL66AL66BL66CL76AL76BL76CL86AL86BL86C

Part93C46A93C46B93C46C93C56A93C56B93C56C93C66A93C66B93C66C93C76A93C76B93C76C93C86A93C86B93C86C

Line 1 Marking

C46AC46BC46CC56AC56BC56CC66AC66BC66CC76AC76BC76CC86AC86BC86C

Temperature range on second line.

93XX46X/56X/66X/76X/86X

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]Note:For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packagingNNOTE 1E112D3EA2AA1eb1bLceBUnitsDimension LimitsNumber of PinsPitchTop to Seating PlaneMolded Package ThicknessBase to Seating PlaneShoulder to Shoulder WidthMolded Package WidthOverall LengthTip to Seating PlaneLead ThicknessUpper Lead WidthLower Lead WidthOverall Row Spacing §NeAA2A1EE1DLcb1beB–.115.015.290.240.348.115.008.040.014–MININCHESNOM8.100 BSC–.130–.310.250.365.130.010.060.018–.210.195–.325.280.400.150.015.070.022.430MAXNotes:1.Pin 1 visual index feature may vary, but must be located with the hatched area.2.§ Significant Characteristic.3.Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010\" per side.4.Dimensioning and tolerancing per ASME Y14.5M.BSC: Basic Dimension. Theoretically exact value shown without tolerances.MicrochipTechnologyDrawingC04-018BDS21929D-page 26© 2007 Microchip Technology Inc.

93XX46X/56X/66X/76X/86X

8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC]Note:For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packagingDeNEE1NOTE 1123bhφchαAA2A1LL1βUnitsDimension LimitsNumber of PinsPitchOverall HeightMolded Package ThicknessStandoff §Overall WidthMolded Package WidthOverall LengthChamfer (optional)Foot LengthFootprintFoot AngleLead ThicknessLead WidthMold Draft Angle TopMold Draft Angle BottomNeAA2A1EE1DhLL1φcbαβ0°0.170.315°5°0.250.40–1.250.10MINMILLIMETERSNOM81.27 BSC–––6.00 BSC3.90 BSC4.90 BSC––1.04 REF–––––8°0.250.5115°15°0.501.271.75–0.25MAXNotes:1.Pin 1 visual index feature may vary, but must be located within the hatched area.2.§ Significant Characteristic.3.Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.4.Dimensioning and tolerancing per ASME Y14.5M.BSC:Basic Dimension. Theoretically exact value shown without tolerances.REF:Reference Dimension, usually without tolerance, for information purposes only.MicrochipTechnologyDrawingC04-057B© 2007 Microchip Technology Inc.DS21929D-page 27

93XX46X/56X/66X/76X/86X

8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]Note:For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packagingeNLDNbKEE2EXPOSED PADNOTE 112D2TOP VIEWBOTTOM VIEW21NOTE 1AA3A1NOTE 2UnitsDimension LimitsMINMILLIMETERSNOM80.50 BSC0.800.000.900.020.20 REF2.00 BSC3.00 BSC1.301.500.180.300.20––0.250.40–1.751.900.300.50–1.000.05MAXNumber of PinsPitchOverall HeightContact ThicknessOverall LengthOverall WidthExposed Pad LengthExposed Pad WidthContact WidthContact LengthContact-to-Exposed PadNeAA3DED2E2bLKStandoff A1Notes:1.Pin 1 visual index feature may vary, but must be located within the hatched area.2.Package may have one or more exposed tie bars at ends.3.Package is saw singulated.4.Dimensioning and tolerancing per ASME Y14.5M.BSC:Basic Dimension. Theoretically exact value shown without tolerances.REF:Reference Dimension, usually without tolerance, for information purposes only.MicrochipTechnologyDrawingC04-123BDS21929D-page 28© 2007 Microchip Technology Inc.

93XX46X/56X/66X/76X/86X

6-Lead Plastic Small Outline Transistor (CH or OT) [SOT-23]Note:For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packagingbN4EE1PIN 1 ID BYLASER MARK12ee1D3AA2cφA1LL1UnitsDimension LimitsMINMILLIMETERSNOM60.95 BSC1.90 BSC0.900.890.002.201.302.700.100.350°0.08––––––––––1.451.300.153.201.803.100.600.8030°0.26MAXNumber of PinsPitchOutside Lead PitchOverall HeightMolded Package ThicknessStandoffOverall WidthMolded Package WidthOverall LengthFoot LengthFootprintFoot AngleLead ThicknessNee1AA2A1EE1DLL1φcLead Widthb0.20–0.51Notes:1.Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.2.Dimensioning and tolerancing per ASME Y14.5M.BSC:Basic Dimension. Theoretically exact value shown without tolerances.MicrochipTechnologyDrawingC04-028B© 2007 Microchip Technology Inc.DS21929D-page 29

93XX46X/56X/66X/76X/86X

8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]Note:For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packagingDNEE1NOTE 112ebAA2cφA1UnitsDimension LimitsNumber of PinsPitchOverall HeightMolded Package ThicknessOverall WidthMolded Package WidthOverall LengthFoot LengthFootprintFoot AngleLead ThicknessLead WidthNeAA2EE1DLL1φcbL1MILLIMETERSMINNOM80.65 BSC–0.750.00–0.85–4.90 BSC3.00 BSC3.00 BSC0.400°0.080.220.600.95 REF–––8°0.230.400.801.100.950.15MAXLStandoff A1Notes:1.Pin 1 visual index feature may vary, but must be located within the hatched area.2.Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.3.Dimensioning and tolerancing per ASME Y14.5M.BSC:Basic Dimension. Theoretically exact value shown without tolerances.REF:Reference Dimension, usually without tolerance, for information purposes only.MicrochipTechnologyDrawingC04-111BDS21929D-page 30© 2007 Microchip Technology Inc.

93XX46X/56X/66X/76X/86X

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]Note:For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packagingDNEE1NOTE 11b2ecAA2φA1L1LUnitsDimension LimitsNumber of PinsPitchOverall HeightMolded Package ThicknessOverall WidthMolded Package WidthMolded Package LengthFoot LengthFootprintFoot AngleLead ThicknessLead WidthNeAA2EE1DLL1φcb0°0.090.194.302.900.45–0.800.05MINMILLIMETERSNOM80.65 BSC–1.00–6.40 BSC4.403.000.601.00 REF–––8°0.200.304.503.100.751.201.050.15MAXStandoff A1Notes:1.Pin 1 visual index feature may vary, but must be located within the hatched area.2.Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.3.Dimensioning and tolerancing per ASME Y14.5M.BSC:Basic Dimension. Theoretically exact value shown without tolerances.REF:Reference Dimension, usually without tolerance, for information purposes only.MicrochipTechnologyDrawingC04-086B© 2007 Microchip Technology Inc.DS21929D-page 31

93XX46X/56X/66X/76X/86X

NOTES:

93XX46X/56X/66X/76X/86X

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93XX46X/56X/66X/76X/86X

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93XX46X/56X/66X/76X/86XDS21929DDevice: Literature Number: Questions:

1.What are the best features of this document?

FAX: (______) _________ - _________

2.How does this document meet your hardware and software development needs?

3.Do you find the organization of this document easy to follow? If not, why?

4.What additions to the document do you think would enhance the structure and subject?

5.What deletions from the document could be made without affecting the overall usefulness?

6.Is there any incorrect or misleading information (what and where)?

7.How would you improve this document?

93XX46X/56X/66X/76X/86X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

EEPROM

VoltageSeries93AA = 1.8V-5.5VLC = 2.5V-5.5VC = 4.5V-5.5V

46 = 1 Kbit56 = 2 Kbit66 = 4 Kbit76 = 8 Kbit86 = 16 Kbit

A = x8 bitB = x16 bitC = Selectable

Blank = Std PkgT = Tape & Reel

I = -40°C to +85°CE = -40°C to +125°C

P = 8-Lead PDIP

SN = 8-Lead SOIC (3.90 mm)MC = 8-Lead 2x3 DFNCH or OT = 6-Lead SOT-23

MS = 8-Lead MSOPST = 8-Lead TSSOP

WordSizeTape &ReelTempRangeDensityPackageExamples:a)b)c)d)

93AA46A-I/MS: 1K, 128x8 Serial EEPROM,Industrial Temperature, MSOP package, 1.8V93AA46BT-I/OT: 1K, 64x16 Serial EEPROM,SOT-23 package, tape and reel, 1.8V

93AA46CT-I/MS: 1K, 128x8 or 64x16 SerialEEPROM, MSOP package, tape and reel, 1.8V93AA46BX-I/SN: 1K, 128x8 Serial EEPROM,Industrial temperature, SOIC package (alter-nate pinout), tape and reel package, 1.8V

93LC66A-I/MS: 4K, 512x8 Serial EEPROM,MSOP package, 2.5V

93LC66BT-I/OT: 4K, 256x16 Serial EEPROM,SOT-23 package, tape and reel, 2.5V

93C86AT-I/OT: 16K, 2048x8 Serial EEPROM,SOT-23 package, tape and reel, 5.0V

93C86BT-I/OT: 16K, 1024x16 Serial EEPROM,SOT-23 package, tape and reel, 5.0V

93C86CT-I/MC: 16K, 2048x8 or 1024x16Serial EEPROM, DFN Industrial temperature,tape and reel package, 5.0V

e)f)g)h)i)

93XX46X/56X/66X/76X/86X

NOTES:

Note the following details of the code protection feature on Microchip devices:•••

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

••

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PROMATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

WORLDWIDE SALES AND SERVICE

AMERICAS

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12/08/06

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